AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet - Page 9

• Manufacturer Part Number: AN2333
• Description: Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs
• Manufacturer: Freescale Semiconductor / Motorola

2.2.4 Interrupt controller
2.2.5 FCC Driver/Interrupt Handler
2.2.6 Timer and Statistics
2.3 Software Configuration Options
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The PIC also manages the priorities among the rest of the MSC8101 peripherals.
The interrupt controller used here is basic, but it performs all the required tasks: context saving, interrupt
source determination, interrupt handler address match plus execution, and context restoring. Before the
MSC8101 device enters normal run-time mode, the interrupt controller configures the MSC8101
programmable interrupt controller (PIC) and SIU-CPM interrupt controller (SIC) to handle both edge and
triggered interrupts. The interrupt controller features a C switch to use either complete or reduced context
saving/restoring. The reduced context switching requires fewer cycles, but also requires interrupt
handlers to use a reduced set of SC140 registers. You can write the interrupt handlers in assembly
language or use compiler options to do so.
As Figure 4 shows, interrupts are generated by FCCs and then transmitted to the SIC, which manages
priorities for serial DMA (SDMA) and CPM peripherals. Then the (PIC) manages the interrupt.
the interrupt arrives at the SC140 core.
The FCC interrupt handler is a short function that first determines the type of the interrupt (received or
transmitted frame/buffer, frame discarded, and so on). Its decision logic section depends on the
application. In our application, it simply receives and sends frames without any treatment. In other
applications, this decision logic might handle buffer management or other tasks. Frame management
occurs through the buffer descriptors (BDs), which indicate the buffer to transmit, the received frame, and
so on. The interrupt handler acknowledges an interrupt by setting to the appropriate bits to a value of 1.
The BD is a memory space to which both the FCC driver and the CPM FCC have access. This memory
space can be mapped to a C structure for convenience. A BD contains a set of information on each
transmit and receive buffer, such as status (16 bits to set attributes), size (in bytes), and address (pointer to
the start of the buffer).
In conjunction with the interrupt controller, there is a C switch to use either complete or reduced context
saving/restoring. These two switches must both be set or cleared.
A timer displays the RMON frame counters on the IDE I/O window every 10 seconds. The procedure for
initializing this timer is much like that for initializing FCCs. During initialization, the timer registers are
configured, and the timer interrupt handler is connected to the interrupt controller. The timer period is
crystal-dependent, so a check of the on-board crystal is required. Any changes to the crystal or to
MODCLK should be reflected in the appropriate files.
This section discusses the files containing the global parameters, with listings of the default values, which
provide the best throughput.
• 2FCCs.h. Enable/disable FCC1 or FCC2:
#define FCC1_ENABLED 1
#define FCC2_ENABLED 1
#define FCC1_RX_ENABLED 1
#define FCC2_RX_ENABLED 1
#define FCC1_TX_ENABLED 1
#define FCC2_TX_ENABLED 1
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
2FCCs Project
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At last,
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