AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet - Page 13

• Manufacturer Part Number: AN2333
• Description: Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs
• Manufacturer: Freescale Semiconductor / Motorola

3.5 FCC Interrupt Handler
The ISR decision logic is implemented through either the SIU Interrupt Vector Register (SIVEC) or
through the SIU Interrupt Pending Register (SIPNR_H and SIPNR_L), as follows:
• SIVEC. This register contains a 6-bit code representing the unmasked interrupt source of the highest
• SIPNR_H and SIPNR_L. Each bit in the interrupt pending registers corresponds to an interrupt source.
On most compilers, the ISR is defined by adding a line in the source code just before the function
definition, as follows:
"#pragma interrupt Name_of_the_ISR_function"
An interrupt handler function differs from other functions in two main ways. Context saving and
restoring surrounds the ISR function, and it runs in Exception mode, forcing the compiler to generate
instructions that differ slightly from the instructions issued in Normal mode.
For the 2FFC project, the FCC interrupt handler is a simple BD manager. In a complete system, it would
also provide hooks for upper protocol layers (software) and function as the entry point for a payload
fabric. The coding language is either assembly or C. The use of assembly language permits a reduction in
SC140 core cycles and is required when the ISR is working with reduced context switching. Assembly
code is a great source of errors, especially for the ISR, so care must be taken in writing Assembly code.
The C language is the default option and is more portable and more easily maintainable.
There are many possible buffer servicing methods for the interrupt handler. Calls to the FCC interrupt
handler consume SC140 core cycles. The servicing method directly determines the ISR call frequency.
Thus the choice of the servicing method and the FCC interrupt handler design are critical in a system
design. Buffers can be serviced one at a time so that each received or transmitted buffer generates an
interrupt. This method can result in a non-serviced buffer, which then breaks the BD rings and stops
reception or transmission. Such breakages can occur at high throughputs as more than one buffer can be
transmitted or received between two FCC Interrupt handler calls.
Alternatively, all buffers can be serviced at once so that each received or transmitted buffer generates an
interrupt. This method consumes many SC140 core cycles but ensures that all buffers are serviced so that
no BD rings are broken. Yet a third buffer service option is to use a minimum FCCINTHandler in
conjunction with dynamic buffer allocation/management. A flag/semaphore and separate handler
launched by scheduler/RTOS can also be added to decrease the cycles spent in the handler, thus
improving the real-time aspect of the global system.
The goal of the 2FCCs project is to provide a simple example with high Ethernet throughput. Therefore,
it implements the method of servicing the buffers one at a time because of its simplicity. In real, more
complex systems, using a minimum FCCINTHandler in conjunction with dynamic buffer
allocation/management (or a similar schema) would be necessary because of the flexibility. The
maximum reachable throughput should be similar, regardless of the buffer servicing method.
Note:
priority level. Use of SIVEC results in interrupt service that is generic and independent of peripherals.
When an interrupt is received, the interrupt controller sets the corresponding SIPNR bit. These
registers are used in conjunction with their respective mask (SIMR_H and SIMR_L). Use of these
registers can slightly improve performance.
For the reasons provided here, the FCC interrupt handler should reduce its access to FCCE and
other DPRAM registers/memory areas to a minimum and make use of optimized code.
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Performance
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