AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet - Page 11

• Manufacturer Part Number: AN2333
• Description: Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs
• Manufacturer: Freescale Semiconductor / Motorola

3.2 Buffers
because read or write requests must cross the Q2PPC bridge and the system bus/local bus bridge. This
requirement directly affects MSC8101 internal bus loading and global system speed, as well as all
memory space to be accessed by both the SC140 core and the CPM, such as buffers and buffer
descriptors.
The MSC8101 buffers enable data transfers to/from the CPM and FCC and to/from memory through
SDMA transactions that are transparent to the user. Buffers can be located in three types of memory:
• Internal SRAM. Provides rapid one-cycle access to the buffer.
• External SDRAM. Accesses to the buffer consume more SC140 core cycles but free the internal
• Internal DPRAM. This is the right choice for applications in which the SC140 core does not access the
In a complete MSC8101-based embedded system, the choice of memory location for buffers is a trade-off
based upon the available internal SRAM and SDRAM space, frame latency, load on the system bus/local
bus, and so on. Buffers can be 4-bye aligned or not, depending on memory space allocation. CPM
communications channels (SCC, MCC, FCC) access their buffers and BDs via SDMA. As for all DMA
data transfers, the alignment on a 4-byte boundary (for 32-bit systems such as the MSC8101) provides the
best performance.
For the 2FCC project, these values yield the best balance between SRAM consumption and throughput.
More buffers on the receive side allow a greater burst of frame; more buffers on the transmit side allow
larger frame burst generation. Of course, allocating fewer buffers for both receiving and transmitting data
saves memory space.
To simplify buffer management, allocate one buffer for one frame rather than several buffers for one
frame. This practice increases buffer size so that the use of memory space is less flexible. However,
depending on the Ethernet protocol, if a partial chunk checksum must be computed (such as for IP and
UDP), allocating one buffer per frame results in faster and simpler algorithms because the data is always
contiguous.
We set buffer size to 1500 (Ethernet MTU) + 18 (Ethernet encapsulation). When the system is connected
to an unfamiliar environment, this is the safest choice. When the system is connected to an entirely
defined environment, setting the buffer size to a known maximum frame size saves memory space. If you
are allocating several buffers to one frame, you can set the size to a smaller value than the known
maximum frame size (for example, 64 bytes). Because the 2FCCs project must handle frame sizes in the
range of 64–1500 bytes, it is mandatory that we set the buffer size to 1500 (Ethernet MTU) + 18 (Ethernet
encapsulation).
Note:
memory so that the payload fabric can work in temporary space in the internal SRAM while DMA
transfers occur to/from external SDRAM. This use of memory space increases the frame latency.
data and directly forward it to a CPM communications channel. Otherwise, it offers no advantages.
This choice has an impact on the RSTATE register in the FCC common parameters.
Once the BD that points to a buffer is full or not empty (for transmit buffers) or empty or not
fully (for receive buffers), neither the SC140 core nor any MSC8101 peripherals should write or
even read the contents of the buffer. Doing so may result in a crash and freeze of the CPM
and/or SC140 core.
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Performance
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