AN2333 Freescale Semiconductor / Motorola, AN2333 Datasheet - Page 10

• Manufacturer Part Number: AN2333
• Description: Maximizing the Performance of Two Fast Ethernet Links on MSC8101 FCCs
• Manufacturer: Freescale Semiconductor / Motorola

Performance
3
3.1 Accesses to MSC8101 Internal SRAM
10
Performance
• Timer.h. Reflects the value of the on-board crystal:
• Payload.h. Sets the frame size:
• FCCs_Int_Handler.h. Uses the hand-optimized ASM (reduced register set) or C version:
• FCC1_ENET.h and FCC2_ENET.h. Sets or unsets the internal loopback, sets the FCC MAC
• IRQ.h. Specifies normal or reduced context switching:
The parts of the 2FCCs project that can remain as is are as follows:
• Most of the initialization for the board
• Most of the initialization for the Ethernet PHY
• Most of the initialization for the FCCs
• The interrupt controller in normal mode
The parts of the 2FCCs project that may need to be changed and adapted are as follows:
• Buffer descriptor initialization
• Buffer management
MSC8101 target markets include media (voice/fax/data) over packet gateways. In such embedded
systems, packet traffic is characterized by moderate to high bandwidth consumption. Packets are usually
shorter than 250 bytes. On MSC8101 Ethernet links, this traffic has an impact on frequency interrupt,
final throughput, and packet latency. This section discusses how to optimize the Ethernet parameter
values. Modifications may be needed if the Ethernet network traffic differs from that described here.
The SC140 core should use
requires one cycle. In contrast, accessing SRAM via
bus requires many more cycles. The
reconfigured. Read or write operations can consume up to four bus cycles, and assuming an SC140
core/bus speed ratio of 5 (MODCLK 40), such operations may require up to 20 SC140 core cycles
#define DIV16
#define BRG_VALUE 306
#define FRAME_SIZE_1 64
#define FRAME_SIZE_2 64
#define INTHANDLER ASM
address, and determines the number and the size of buffers for both the transmit and receive paths:
#define FCCx_INTLPBK 0
#define ENETx_PADDR_H
#define ENETx_PADDR_M
#define ENETx_PADDR_L
#define FCCx_TX_BUF_SIZE
#define FCCx_RX_BUF_SIZE
#define FCCx_TX_NUM_BUF
#define FCCx_RX_NUM_BUF
#define OPTIMIZATIONS ON
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CS0
1
at memory offset 0x0 to access the internal SRAM. Such an access
CS0
setting at a memory offset of 0x0 is the default, which can be
// refer to the table
// must be an even number
// must be an even number
// C
//1
0x00E0
0x0C12
0x3472
0x5EE //1518 in decimal
0x5EE //1518 in decimal
4
4
CS10
//Physical Addr.1 (MSB)
//Physical Addr.1
//Physical Addr.1 (LSB)
at memory offset 0x02000000 on the system