AN2254 Freescale Semiconductor / Motorola, AN2254 Datasheet - Page 9

• Manufacturer Part Number: AN2254
• Description: Scrambling Code Generation for WCDMA
• Manufacturer: Freescale Semiconductor / Motorola

These are the overall steps performed to generate the binary PN code in mainloop. The mainloop iterates 2400
times, producing 16-bit samples of c1 and c2 in each iteration. As a result, 38400 chip segments are produced.
3.3 Forming the Complex Scrambling Sequences
Once the binary PN code is generated, the next step is the formation of complex scrambling sequences from the
binary PN code. Complex scrambling code is formed according to Equation 12 or Equation 13 and Equation 14.
According to these equations, every other sample of c2 binary PN code is selected before the formation of complex
scrambling code. After a 16-bit binary scrambling sequence is formed, it is mapped into a real-valued code
according to Equation 9 on page 5, one bit at a time. This occurs in the mappingloop section of the program. This
part of the code takes the 16-bit c1 and c2 samples and forms complex scrambling codes, 16 bits at a time.
According to Equation 12, the real part of the scrambling sequence is c1 itself, and no change is required for
calculating the real part of the scrambling sequence. The complex part of the scrambling sequence is a
multiplicative result of the real valued code of c1,c2 and +1 or -1, depending on whether it is an even or odd
Freescale Semiconductor
3.
4.
— 7-bit shifted D6 (X7-instruction set ‘d’)
— 18-bit shifted D6 (X18-instruction set ‘h’)
— 4-bit shifted D7 (Y4-instruction set ‘d’)
— 6-bit shifted D7 (Y6-instruction set ‘e’)
— 17-bit shifted D7 (Y17-instruction set ‘i’)
The first 16-bit sample for c2 is determined in instruction set ‘j’ of code listing 3 and then stored in the
memory buffer in the very next instruction set ‘k’.
Since the algorithm determines 16-bit samples and then shifts out the lower 16 bits from data registers
D6 and D7, the determination of the feedback polynomials, X25 and Y25, is required:
a.
b.
c.
d.
After the feedback polynomials (X25 and Y25) have been determined and the original registers (D6
and D7) are shifted by 16 bits, we put the significant 16 bits of the 25-stage LFSRs into place. This
occurs in cycles ‘e,’ ‘f,’ ‘g,’ and ‘h:’
a.
b.
c.
d.
Scrambling Code Generation for WCDMA on the StarCore™ SC140/SC1400 Cores, Rev. 1
The feedback polynomial X25 is a modulo 2 sum of the non-shifted lower 16 bits of D6 (X0
instruction set ‘a’ and ‘h’) and a 3-bit shifted version of D6 (X3 instruction set ‘b’ and ‘i’).
The first feedback X25 polynomial is determined in instruction set ‘c’ and then in instruction set
‘k’ in mainloop and is stored in register D1 in the same instruction set ‘k.’
The feedback polynomial Y25 is a modulo 2 sum of the non-shifted lower 16 bits of D7 (Y0
instruction set ‘a’ and ‘i’), 1-bit shifted D7 (Y1 instruction set ‘a’ and ‘i’), 2-bit shifted D7 (Y2
instruction set ‘b’ and ‘j’), and a 3-bit shifted D7 (Y3 instruction set ‘c’ and ‘k’).
The first feedback Y25 polynomial is determined in instruction set ‘d’ and stored in register D9 in
the same cycle.
In instruction set ‘e,’ the lower 16 bits of the feedback polynomials (X25 and Y25) are extracted
and stored in D1 and D9.
In instruction set ‘f,’ the lower 16 bits of D1 and D9 are shifted to the left by 9, so that they
become the higher 16 bits of a 25-stage LFSR.
In instruction set ‘g,’ D6, which by now has shifted out its lower 16 bits and has only 9 bits located
in its least significant part, gets the higher 16 bits from D1.
Similarly, in instruction set ‘h,’ D7 gets its higher 16 bits from D9 for its 25-stage LFSR without
affecting its lower 9 bits.
Software Implementation on the StarCore SC140/SC1400 Cores
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