AN2254 Freescale Semiconductor / Motorola, AN2254 Datasheet - Page 7

• Manufacturer Part Number: AN2254
• Description: Scrambling Code Generation for WCDMA
• Manufacturer: Freescale Semiconductor / Motorola

3.2 Binary PN Code and Complex Scrambling Sequences
For optimal implementation of the algorithm to generate the complex binary PN code, 16 stacked-bit samples are
generated in one iteration rather than generating the PN code one bit at a time. Since a PN code is essentially a
system of LFSRs, the last 16 bits are processed in one operation to give 16 samples of PN code. Example 1 shows
the pseudo code for this implementation.
X= Upper LFSR
Y= Lower LFSR
for (i = 0; i < 2400; i++)
poly.
poly.
poly.
poly.
Freescale Semiconductor
Global Variable Name
OUTPUT_IQ
X0
X3
X4
X7
X25 =
X = (X >> 16)
X = (X | (X25 << 9)) ;//most sig. 9 bits from prev iteration & 16 sig bits from this iteration
X18 = (X >> 2)
Y0
Y1
Y2
Y3
Y4
Y6
Y25 = (Y3 ^ Y2 ^ Y1 ^ Y0) ;//feedback polynomial, accodring to eqn. 7, most significant 16 bits
Y = (Y >> 16)
Y = (Y | (Y25 << 9)) ;//most sig. 9 bits from prev iteration & 16 sig bits from this iteration
Y17 = (Y >> 1)
INPUT_IQ
CODE_IQ
=
=
=
=
= (Y >> 0)
= (Y >> 1)
= (Y >> 2)
= (Y >> 3)
= (Y >> 4)
= (Y >> 6)
Scrambling Code Generation for WCDMA on the StarCore™ SC140/SC1400 Cores, Rev. 1
(X >> 0)
(X >> 3)
(X >> 4)
(X >> 7)
(X3 ^ X0)
Points to the interleaved complex scrambling code. This
scrambling code is stored as a real-valued code scaled
down by a factor of 2 (+1 as +0.5 or -1 as -0.5). Since the
code length for a frame is 38400 chip segments, each
sample is stored as a 16 bit sample, and each chip segment
contains an I and Q part, a buffer of 38400*2*2 bytes is
assigned.
Points to the buffer in the memory where the interleaved
input data to be scrambled is stored. This assembly code
assumes that the data samples are 16-bits wide and are
held in the memory buffer as I/Q interleaved samples.
Points to the memory buffer where the interleaved
scrambled data is stored for one frame.
Example 1. Pseudo Code for 16-Bit Vector Processing
;//(38400/16) = 2400
{
;//X0 holds the lower 16 bits of X non-shifted, reqd for c1 & X25 feedback
;//X3 holds the lower 16 bits of X shifted by 3,reqd for X25 feedback
;//X4 holds the lower 16 bits of X shifted by 4, reqd for c2
;//X7 holds the lower 16 bits of X shifted by 7, reqd for c2
;//feedback polynomial, accodring to eqn. 6, most significant 16 bits
;//for next iteration, 9 from previous iteration, as old 16 shifted out
;//lower 16 bits shifted out
;//X is ready for next
;//X18 holds the lower 16 bits of X shifted by 18, reqd for c2
;//Y0 holds the lower 16 bits of Y non-shifted, reqd for c1 & Y25 feedback
;//Y1 holds the lower 16 bits of Y shifted by 1, reqd for Y25 feedback
;//Y2 holds the lower 16 bits of Y shifted by 2, reqd for Y25 feedback
;//Y3 holds the lower 16 bits of Y shifted by 3, reqd for Y25 feedback
;//Y4 holds the lower 16 bits of Y shifted by 4, reqd for c2
;//Y5 holds the lower 16 bits of Y shifted by 6, reqd for c2
;//lower 16 bits shifted out
;//Y is ready for next
;//X17 holds the lower 16 bits of Y shifted by 17, reqd for c2
;//for next iteration, 9 from previous iteration, as old 16 shifted out
Table 1. Memory Allocation
Description
Software Implementation on the StarCore SC140/SC1400 Cores
Number of Bytes
38400 × 2 × 2
38400 × 2 × 2
38400 × 2 × 2
7