AN2254 Freescale Semiconductor / Motorola, AN2254 Datasheet - Page 8

• Manufacturer Part Number: AN2254
• Description: Scrambling Code Generation for WCDMA
• Manufacturer: Freescale Semiconductor / Motorola

Software Implementation on the StarCore SC140/SC1400 Cores
Now, the formation of the complex scrambling codes begins. In this part of the code, the C/Assembly calling
function enters the assembly code, and the data variables and pointers are put into the appropriate registers for the
assembly function to use. The pn_generation subroutine includes the pn_generation_param.asm parameter file,
which defines the local constants used by this subroutine:
Data registers D6 and D7 are the two 25-stage LFSRs. Since the LFSRs are only 25-stage, only the lower 25 bits of
the data registers are used for this purpose. The most significant 15-bits are set to zero (data registers are 40 bits
wide). The first three instructions initialize the lower LFSR and the upper LFSR as shown in Figure 3 according to
the initialization value that is stored in global variable REG1 for the upper LFSR (see Example 2). The last
instruction loads address register R0 to point to the memory buffers to store the interleaved scrambling code
samples I and Q.
The program can be divided into two main parts:
3.2.1 Generating the Binary PN Code
Generating the binary PN codes as stacked bits is accomplished following the algorithm shown in Example 1. The
mainloop in the program generates the PN codes. The mainloop produces 16-bit stacked c1 and c2 PN code
samples, as shown in Figure 3. As the routine starts, it executes instructions to set up the address and data registers
before the code jumps into mainloop. The code sets up mainloop and the loop counter for the loop to perform 2400
iterations, as described in Example 3 (which shows a complete assembly code listing for generating the PN codes
and the function for forming complex scrambling sequences, pn_generation.asm). Following is a step-by-step
description of one iteration of the StarCore DSP code to demonstrate how it executes:
8
c1 = (X0 ^ Y0)
c2 = (X4 ^ X7 ^ X18 ^ Y4 ^ Y6 ^ Y17) ;//16-stacked bit c2 according to figure 3 configuration
}
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•
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1.
2.
1.
2.
REG2_INIT holds the value 0x01FFFFFF for initializing the lower 25-stage LFSR, as shown in
Figure 3.
MASK16 holds the value 0x000000FFFF for masking the lower 16-bits of a data register.
NUM_ITER specifies the number of times the main loop in the function iterates. It is initialized to
2400.
Generating the binary PN code.
Forming the complex scrambling sequence.
To determine c1and c2 for the PN code, we must determine the polynomials that are required. The c1
part of the PN code is a modulo 2 sum of the least significant bits of the X and Y registers.
a.
b.
Determining c2 requires a modulo 2 sum of several shifted polynomials:
— 4-bit shifted D6 (X4-instruction set ‘c’ and ‘k’)
Scrambling Code Generation for WCDMA on the StarCore™ SC140/SC1400 Cores, Rev. 1
The first 16-bit c1 sample is determined in instruction set ‘b’ of Example 3.
Inside the mainloop, it is calculated in instruction set ‘j’ and stored into the memory buffer in
instruction set ‘d’.
move.l
move.l
move.l
move.l
will be
Example 2. Setting Data and Address Registers
#REG1,r0
#REG2_INIT,d7
(r0),d6
#CODE_IQ,r0
stored
;//16-stacked bit c1 according to figure 3 configuration
;//R0 points to initial value of upper LFSR
;//D7 is the lower LFSR
;//D6 is the upper LFSR
;//R0 points to where IQ scrambling code
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