AN2254 Freescale Semiconductor / Motorola, AN2254 Datasheet - Page 6

• Manufacturer Part Number: AN2254
• Description: Scrambling Code Generation for WCDMA
• Manufacturer: Freescale Semiconductor / Motorola

Software Implementation on the StarCore SC140/SC1400 Cores
2.2 Scrambling an I-Q/Code Multiplexed Signal
Figure 2 shows that before the data signal is QPSK modulated, the I-Q/code multiplexed data signal is multiplied
with the complex scrambling code. In this step, the two complex signals are multiplied together as shown in the
following equations, where DI = the real part of the incoming data:
Where:
Equation 15 implies the final result, as follows:
3
This section describes how the algorithms in Section 2, Scrambling Codes for WCDMA, are implemented on the
StarCore SC140/SC1400 DSP cores. For ease of implementation, the algorithms slightly differ from the theory
presented in Section 2. The first part of the program generates the PN code, and the second part performs the actual
scrambling of the incoming signal. First, the memory space required for these calculations is specified.
3.1 Allocating Memory Space
The assembly code assumes that required memory space has been allocated before the assembly routine is called.
This memory space is 16-bit aligned. Table 1 lists the exact amount of space required for different global variables.
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Global Variable Name
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SC140/SC1400 Cores
Software Implementation on the StarCore
REG1
DI = real part of the incoming data
DQ = complex part of the incoming data
SI = real part of the scrambling code
SQ = complex part of the scrambling code
I = 0, 1, 2, . . . , 38399
Scrambling Code Generation for WCDMA on the StarCore™ SC140/SC1400 Cores, Rev. 1
Holds the starting phase value for PN code generation. As
shown in Equation 3, the PN code generated depends on
the initial value of the 25-stage LFSR. The most significant
bit of the upper 25-stage LFSR is always one (1), and the
initial value for this register is passed to the assembly code.
The lower 25-stage LFSR does not require initialization
because all of its 25 bits are always configured to a value of
one (1) at the start of a new sequence.
( DI i + jDQ i ) x ( SI i + jSQ i )
(( DI i *SI i ) – ( DQ i *SQ i )) + j(( DI i *SQ i ) + ( DQ i *SI i ))
Table 1. Memory Allocation
Description
Freescale Semiconductor
Number of Bytes
4
Equation 15
Equation 16