AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 9

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

3.2 DMA Set-Up
3.2.1 Mode for HDI16 DMA Signals
3.2.2 DMA Buffers and Buffer Descriptors
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For information on buffer descriptors, consult the Overview chapter of the MSC8101 User’s Guide or the application
note entitled Initializing MSC8101 CPM Parameter RAM and Buffer Descriptors (AN2147). The format of the buffer
descriptors used in DMA transactions is described in the “Programming Model” section of the DMA chapter in the
MSC8101 Reference Manual.
MSC8101 software. Consequently, the HDI16 HDI16 side acts as a master during the synchronization
process. When the HDI16-side software is ready to process commands sent from the host, it sets
signal to the host that it is awaiting a synchronization acknowledgment. The host acknowledges
synchronization by sending back
synchronized.
Setting up the DMA receive engine involves three main steps:
1. Selecting the mode for HDI16 DMA signals.
2. Initializing the DMA buffers and buffer descriptors.
3. Setting up and operating DMA interrupts.
The HDI16 can provide DMA signals in two different modes: Single-Request mode (
Double-Request mode (
order to provide the external host with differentiated receive and transmit direction signals to run DMA
data transfers efficiently and transparently. To enable Double-Request mode after power-up, a sequence
bit (BCSR0/1) must be set up appropriately in the Board Control and Status Registers of the appropriate
ADS board. The BCSRx, which are 32-bit read/write registers, control or monitor most of the hardware
options on the ADS. The BCSRx reside on the system bus and are accessible through the MSC8101
memory controller.
Buffer descriptors manipulate buffers and are located in the DMA Channel Parameters RAM (DCPRAM)
space.
• BD_ADDR. This field holds the buffer address pointer. If the buffer is defined as cyclic, the original
• BD_SIZE. This field contains the remaining size of the buffer. This value is decremented by the
• BD_ATTR. This 32-bit parameter describes the attributes of the channel handling this buffer. By setting
• BD_BSIZE. This field holds the base size of the buffer.
Two different DMA transfer modes can be selected: Flyby mode or Dual-Address mode. In Flyby mode,
a single address transaction is used for the transfer, whereas Dual-Access mode requires a complementary
channel to be configured. Flyby mode is the mode of choice here because it exactly fulfills the
requirements of our application. It is generally used to transfer data between an external peripheral and
address value is restored when the BD_SIZE value reaches zero.
transfer block size each time the DMA controller issues a transaction, until it reaches zero. When
BD_SIZE reaches zero, the original value is restored to the value of BD_BSIZE.
the appropriate bit in this field, we can program the DMA controller to issue an interrupt when the size
reaches zero, meaning that the buffer is terminated/full. This parameter is also used to select the type of
transaction to be initiated by the DMA channel.
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The four parameters attributed to each buffer are:
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HRRQ
/
HTRQ)
HF0
HDI16 Device Configuration, Synchronization, and Set-Up
. Our application uses Double-Request mode (
and
HF1
. Once this sequence completes, the interface is
HRRQ
HREQ
/
/
HTRQ
HACK)
HF4
) in
or
to
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