AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 11

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

4.1 Host Memory Controller
4.2 Host HDI16 Registers
To achieve these states, perform the following steps:
1. Configure the host memory controller to enable mapping of the HDI16 registers in memory.
2. Configure the host HDI16 registers, synchronize the host and HDI16 sides, and enable the HDI16
3. Configure the host I/O ports to enable DMA request lines.
4. Configure the host DMA registers and channel buffer descriptors.
5. Configure the host DMA channels so that HDI16 service requests automatically trigger DMA transfers.
6. Configure the common host DMA parameters.
7. Enable host DMA channels.
The MSC8101 memory controller is used to map each HDI16 host register to a specific memory location.
Bank 6 within the memory controller handles these accesses since this bank is free within the current
MSC8101ADS memory controller set-up. The Base and Option Registers are programmed to map the
HDI16 registers to a base memory address of 0x30000000, select a port size of 16 bits, and enable bursts
to the HDI16.
UPM A is selected to issue the required HDI16 signals, so the RAM array for this UPM must be loaded.
Where possible, UPM A uses burst transfers across the HDI16, but first a burst DMA transfer size must
be selected. Also, the data must be 32-byte aligned in memory. The HDI16 interface timings provided by
UPM A are presented in Section 6. Within the example code, the host-side HDI16 registers are accessed
via a type definition (HPORT) that simply overlays the memory-mapped host register locations.
Once the memory controller is initialized, the HDI16 registers are accessible and configured to meet the
needs of this application (see Figure 2 for a list of these registers). Before initializing any of the
HDI16-specific flags, the host must initialize the HDI16 MSC8101 by transmitting its Reset
Configuration Word, writing a byte value to each successive reset configuration register.
The host then waits for the HDI16 MSC8101 to set a host flag, which indicates that the HDI16 MSC8101
is up and running. To complete this handshake, the host sets a couple of host flags to notify the HDI16
MSC8101 that it is running, too. At this point in the Application source code there is an #if-#else
definition to give users the option of testing their physical HDI16 interconnections via a simple polling
mechanism, instead of directly using the full-blown DMA transfer version of the code. The polling
mechanism operates as a continuous loop composed of the following steps, all performed by the host
MSC8101:
1. Wait for the HDI16 transmit buffer empty flag.
2. Write sixteen 16-bit words to the HDI16 Transmit Word Registers (these are processed as 16 separate
3. Wait for the Receive Data Full flag, which indicates that the HDI16 MSC8101 has data ready.
4. Read sixteen 16-bit words to the HDI16 Receive Word Registers.
5. Compare the data transmitted with the data received and store the number of discrepancies.
Otherwise, DMA mode is selected so the host must configure the HDI16 registers to enable the
and
Service Request signals from the host side.
single-beat transactions, not a burst transfer).
HTRQ
Freescale Semiconductor, Inc.
signals, which automate the DMA transfers.
For More Information On This Product,
Go to: www.freescale.com
Host Device Configuration
HRRQ
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