AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 6

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

System Bus–HDI16 Host Interface
2.4 Host DMA Transfers
6
1
Manual but as CS6 in the MSC8101 Reference Manual.
C1, C3, C6,
This signal is designated as BTOLSC1 in the MSC8101ADS User’s
D[16–D32]
Pin No.
D[6–13]
D[1–3]
B[1–3]
D10
D12
C13
P1
C31, C32
Pin No.
D10
P2
D8
Host MSC8101 Side
Notable features of the connections depicted in Table 1 are as follows:
• One chip select,
• Two separate General-Purpose Strobe Lines (
• Data Lines. The host MSC8101 device’s 60x-compatible bus data lines (
• DMA Request/Service Request Lines. Two separate DMA Request lines (
• Address Lines. The Address lines between the host MSC8101 and the HDI16 MSC8101 connect to
• Ground Lines. To provide the best ground plane while connecting the two MSC8101ADS boards, it is
To prevent the host MSC8101 device from dedicating large amounts of SC140 core resource to polling
and accessing the HDI16 MSC8101 device continually, the HDI16 peripheral can assert service request
interrupts to the host as needed. Two HDI16 request generation modes are available, namely single or
double request modes. In Single Request mode, one signal (
receive and transmit operations, but in Double Request mode, separate requests are possible for transmit
and receive (
Signal Name
MSC8101 to the HDI16 MSC8101 HDI16 port and is connected to the HDI16 chip-select line (
—
—
the HDI16 data lines (
Service Request signals (
enable burst transfers across the HDI16. The connections are defined as follows:
— 60x
— 60x
— 60x
— 60x
highly recommended that all grounds be common and connected together.
EXPGPL3
EXPGPL5
System + CPM Edge Connector
DREQ1
DREQ2
Table 1. Physical MSC8101ADS Interconnects (Continued)
PGPL3
read access and low for write access.
PGPL5
16-bit read or write transaction.
0V
EXPA25
EXPA26
EXPA29
EXPA30
Freescale Semiconductor, Inc.
HTRQ
is programmed to generate the HDI16 read/write line (
is programmed to generate the HDI16 Data strobe (
For More Information On This Product,
CS6
DMA Request 1 (PC22)
DMA Request 2 (PC24)
→
→
→
→
and
Signal Description
UPM GPL Line 3
UPM GPL Line 5
HA0
HA1
HA2
HA3
(or
HRRQ
HDx
Go to: www.freescale.com
Ground
BTOLCS1
HRRQ
).
). Single Request mode has the advantage that it saves on the number of
and
as it is called here), is used to map memory accesses from the host
HTRQ
) on the HDI16.
GPLx
20, 35, 36
P4 = H0
Pin No.
1, 2, 19,
27
28
29
30
) are used in this interface:
HREQ
Signal Name
HRRQ/HACK
HTRQ/HREQ
HRW
HDS
HDI16 MSC8101 Side
HDS
0V
) is used to request service for both
HRW
), which must be asserted every
HDI16 Connector
) which is typically high for a
EXPDx
DREQx
Transmit Host Request OP
Receive Host Request OP
Signal Description
Host Data Strobe
) directly connect to
Host Read/Write
) connect to the
Ground
HCS
).