AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 42

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Memory Subsystem (MSS)
For a 128-Kbyte object, 82.8 percent is left in the L2 cache after one pass, but for a 256-Kbyte object only
slightly less than two-thirds of the structure is left in the L2 cache. However, in both cases the percentage
of the structure left in improves with subsequent strides through the data structure.
3.8.3
The L3 cache is an off-chip SRAM with on-chip cache tags. The MPC7450 supports 1- and 2-Mbyte L3
caches. A 1-Mbyte cache is two-sectored (64-byte lines) and a 2-Mbyte cache is 4-sectored (128-byte lines).
The L3 is 8-way set associative, implying 16,384 lines (1-Mbyte/64 or 2-Mbyte/128) or 2,048 sets
(1-Mbyte/64/8 or 2-Mbyte/128/8).
An access missing in the L3 fetches the required 32-byte sector regardless of the L3 line size. Like the L2,
the L3 uses a random replacement algorithm, the implications of which are described in Section 3.8.2, “L2
Cache Effects.”
3.8.4
The MPC7450 supports alternate sector prefetching from the L2 cache. Because the L2 cache is
two-sectored, an access requesting a 32-byte line from the L1 that also misses in the L2 and the L3, can
generate a prefetch (if enabled) for the alternate sector as needed. As many as three outstanding prefetches
are allowed.
The example shown in Table 3-27 can also be used to illustrate the benefits of hardware prefetching for code
when other software techniques are not applied.
The following example shows timing when the loads miss all levels of the cache hierarchy and go to the
system bus. Hardware prefetching is disabled. The load misses to the bus are serialized by the load miss line
alias stall (instruction 2 on instruction 0).
42
Instr.
No.
0
1
2
3
4
5
0
1
2
3
4
5
lwz r3,0x0(r9)
add r4,r3,r20
lwz r5,0x4(r9)
add r6,r5,r4
lwz r7,0x20(r9)
add r8,r7,r6
lwz r3,0x0(r9)
add r4,r3,r20
lwz r5,0x4(r9)
add r6,r5,r4
lwz r7,0x20(r9)
add r8,r7,r6
Instruction
L3 Cache Effects
Hardware Prefetching
MPC7450 RISC Microprocessor Family Software Optimization Guide
Table 3-29. Timing for Load Miss Line Alias Example
100–102
Freescale Semiconductor, Inc.
E0
E1
E0
D
D
0
I
I
For More Information On This Product,
103
E1
E0
E2
E1
1
I
I
Go to: www.freescale.com
Miss
Miss
104
E1
E0
C
E
2
LMQ0
LMQ0
3–81
Cycle Number
105
E1
E0
C
LMQ0/E2 LMQ0/C
106–184
LMQ0
E1
E0
82
LMQ0/E2 LMQ0/C
185
E1
E0
83
E
LMQ0
186
E1
E0
84
C
E
MOTOROLA
85–99
LMQ0
LMQ0
187
E1
E0
C