AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 36

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Load/Store Unit (LSU)
3.7.2
The pipeline for stores before the data is written to the cache includes several different queues. A store
instruction must go through E0 and E1 to handle address generation and translation. It is then placed in the
three-entry finished store queue (FSQ). When the store is the oldest instruction, it can access the store data
and update architecture-defined resources (store serialization). From this point on, the store is considered
part of the architectural state.
However, before the data reaches the data cache, two write-back stages (WB0 and WB1) are needed to
acquire the store data and transfer it from the FSQ to the 5-entry committed store queue (CSQ). Arbitration
into the data cache from the CSQ is pipelined so a throughput of one store per cycle can be maintained.
During this arbitration and cache write, stores arbitrate into the data cache from the CSQ and stay there for
at least four cycles. Table 3-21 shows pipelining of four stw instructions to the data cache.
Because floating-point stores are not fully pipelined, the bottleneck is at the FSQ, where only one
floating-point store can be executed every 3 cycles. See Table 3-22 for an example execution of four stfd
instructions. Vector stores do not have this problem and are fully pipelined (similar to the integer stores as
shown in Table 3-21).
To avoid floating-point store throughput bottlenecks, strings of back-to-back floating-point stores (like that
shown in Table 3-22) should be avoided. Instead, floating-point stores should be mixed with other
instructions wherever possible. For maximum store throughput, vector stores should be used.
36
stw
stw
stw
stw
Instruction 0
Instr.
No.
0
1
2
3
0
1
2
3
stfd
stfd
stfd
stfd
stfd
stfd
stfd
stfd
Instruction
Store Hit Pipeline
— D
— — D
— — —
D
MPC7450 RISC Microprocessor Family Software Optimization Guide
1
I
E0 E1 FSQ0/C
2
FSQ0/C
I
CSQ0
CSQ1
FSQ1
10
—
—
—
D
0
E0
D
3
I
Freescale Semiconductor, Inc.
Table 3-22. Execution of Four stfd Instructions
CSQ0
FSQ0
For More Information On This Product,
E1
E0
WB0
4
I
11
—
—
Table 3-21. Store Hit Pipeline Example
D
1
I
FSQ0/C
CSQ0
FSQ0
WB0
WB1
Go to: www.freescale.com
E1
E0
E0
12
—
5
D
2
I
FSQ0/C
FSQ0/C
CSQ0
CSQ1
WB1
WB0
E1
E0
13
E1
D
3
6
I
FSQ0/C
FSQ0/C WB0
Cycle Number
CSQ0
CSQ0
WB0
WB1
WB0
E1
E0
14
4
I
7
CSQ0 CSQ0 CSQ0
CSQ1 CSQ1 CSQ1 CSQ0
FSQ0
CSQ0
WB1 CSQ2 CSQ2 CSQ1 CSQ0
WB0
WB1
E1
E0
15
8
5
WB1 CSQ3 CSQ2 CSQ1 CSQ0
CSQ0
CSQ1
FSQ0
FSQ1
WB1
9
E1
16
6
10
FSQ0/C
CSQ0
CSQ0
FSQ1
FSQ2
17
7
11
CSQ0
CSQ0
FSQ0
FSQ1
WB0
18
8
MOTOROLA
12
CSQ0
CSQ0
FSQ0
FSQ1
WB1
19
9
13