AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 10

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Overview of Target Microprocessors
If the branch is either b or bc, a taken branch can get instructions from the BTIC. The BTIC lookup is
automatically performed based on the instruction address of the executing branch, and produces instructions
starting at the branch target address. The BTIC supplies two instructions for that cycle, as opposed to the
normal four from the instruction cache. Indirect branches, such as bcctr or bclr , do not get instructions from
the BTIC. Thus, a taken branch incurs a one-cycle fetch bubble when it executes.
2.3.1.5
A good compiler scheduling model for the MPC750 includes the two-instruction-per-clock-cycle dispatch
limitation, a base model of the CQ with maximum of six instructions with two-instruction-per-clock-cycle
completion limitation, and execution units—SRU, IU1, IU2, FPU, and LSU with typical unit execution
latencies as given in Table 2-1.
A full model incorporates full table-driven latency/throughput/serialization specifications given instruction
by instruction in Appendix A, “MPC7450 Execution Latencies.” The notion of reservation stations
(particularly, the second LSU reservation station) should be added. Rename registers limitations for the
GPRs are also needed to allow more accurate modeling of the load/store-with-update instructions.
2.3.2
The MPC7400 microprocessor is similar to the MPC750 microprocessor. The primary differences include
the following attributes:
Figure 2-4 shows a functional block diagram of the MPC7400.
2.3.2.1
The MPC7400 can dispatch two vector instructions per cycle: one to the VPU and one to the VALU. The
VPU is a single-cycle execution unit unlike the VALU which has three independent subunits, each with
different latencies, as follows:
The VALU can initiate one instruction per cycle to any of these three subunits. After execution begins, these
subunits are fully independent.
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Eight-entry CQ (although rename registers are still limited to six)
Vector units (and instructions), which implement the Altivec extensions to the PowerPC
architecture
Better latency and pipelining on double-precision floating-point operations
Increased pipelining of load/store misses in the LSU
The VSIU subunit handles simple integer and logical operations with single-cycle latency per
instruction.
The VCIU handles complex integer instructions (mostly multiplies) with a latency of three clocks
and a throughput of one instruction per cycle.
The VFPU subunit handles vector floating-point instructions with a latency of four clocks and a
throughput of one instruction per cycle.
MPC7400 Microprocessor
MPC750 Compiler Model
Vector Unit
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
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