CY28405 Cypress Semiconductor, CY28405 Datasheet - Page 11

• Manufacturer Part Number: CY28405
• Description: CK409-Compliant Clock Synthesizer
• Manufacturer: Cypress Semiconductor

Document #: 38-07512 Rev. *B
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Cs1
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
Ce1
CPUC, 133MHz
X1
CPUT, 133MHz
REF, 14.31818
Ci1
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
PWRDWN#
Clock Chip
XTAL
Ci2
X2
Figure 3. Power-down Assertion Timing Waveforms
Ce2
Cs2
3 to 6p
33pF
Pin
Trim
Trace
2.8pF
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitative
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
...................................... using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ............................................. Stray capacitance (trace,etc)
Ci ............. Internal capacitance (lead frame, bond wires etc)
PD# (Power-down) Clarification
The PD# pin is used to shut off all clocks and PLLs without
having to remove power from the device. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the power down state.
PD# – Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPUT) clocks
must be held LOW on their next HIGH to LOW transition. CPU
clocks must be held with CPUT clock pin driven HIGH with a
value of 2x Iref and CPUC undriven as the default condition.
There exists an I
be three-stated during power-down. Due to the state of internal
logic, stopping and holding the REF clock outputs in the LOW
state may require more than one clock cycle to complete
CLe
Total Capacitance (as seen by the crystal)
=
Load Capacitance (each side)
(
Ce1 + Cs1 + Ci1
2
C bit that allows for the CPUT/C outputs to
Ce = 2 * CL - (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
CY28405
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