CY28405 Cypress Semiconductor, CY28405 Datasheet
CY28405
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CY28405 Summary of contents
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... PCIF[0:2] VSS_PCI 2 PCI4 PCI[0:5] PCI5 RESET#/PD# DOT_48 3V66_3/VCH USB_48 VSS_48 VDD_48MHz VDD_48 DOT_48 USB_48 RESET# • 3901 North First Street • CY28405 ® Byte, Word, and Block Read/Write 3V66 PCI REF VDDA 2 47 VSSA 3 46 IREF ...
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... Reset Output I 3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E] input (active LOW). I/O SMBus compatible SDATA. I SMBus compatible SCLOCK. PWR 3.3V Power supply for PLL. GND Ground for PLL. PWR 3.3V Power supply for outputs. GND Ground for outputs. CY28405 Description Page ...
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... Reserved Reserved 0 0 100.0 66 133.3 66 200.0 66 Reserved Reserved CY28405 PLL Gear Constants PCI VCO Freq. (G) 33.6 805.6 24004009.32 33.4 801.6 24004009.32 36.0 864.0 24004009.32 33.7 809.6 24004009.32 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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... Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop CY28405 2 C Page ...
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... Reserved, set = 1 Reserved, set = 1 CPUT/C_ITP Output Enable 0 = Disabled (three-state Enabled CPU(T/C)1 Output Enable Disabled (three-state Enabled CPU(T/C)0 Output Enable 0 = Disabled (three-state Enabled CY28405 Byte Read Protocol Description Start Slave address – 7 bits Write = 0 Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation, bits[6:0] ...
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... Allow control of PCIF1 with assertion of SW PCI_STP 0 = Free Running Stopped with SW PCI_STP Allow control of PCIF0 with assertion of SW PCI_STP 0 = Free Running Stopped with SW PCI_STP PCIF2 Output Enable 0 = Disabled Enabled PCIF1 Output Enable 0 = Disabled Enabled PCIF0 Output Enable 0 = Disabled Enabled CY28405 Description Description Description Page ...
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... Spread Spectrum Enable 0 = Spread Off Spread On REF_1 Output Enable 0 = Disabled Enabled REF_0 Output Enable 0 = Disabled Enabled Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28405 Description Description Description Page ...
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... Vendor Test Mode (always program to 0) Vendor Test Mode (always program to 0) Name PCI skew control 00 = Normal 01 = –500 Reserved 11 = +500 ps 3V66 skew control 00 = Normal 01 = –150 +150 +300 ps Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 CY28405 Description Description Description Page ...
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... When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Name FS_Override 0 = Select operating frequency by FS(E:A) input pins 1 = Select operating frequency by FSEL(4:0) settings Reserved, Set = 1 Reserved, Set = 0 CY28405 Description Description Description Description Page ...
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... Crystal Recommendations The CY28405 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28405 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... Ce2 Trim be three-stated during power-down. Due to the state of internal 33pF logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete CY28405 Load Capacitance (each side (Cs + Ci) Total Capacitance (as seen by the crystal ...
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... Clock State State 0 Off Clock Outputs Off Clock VCO Document #: 38-07512 Rev. *B Tstable <1.8ms Tdrive_PWRDN# <300µs, >200mV 0.2-0.3mS Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On Figure 5. VTT_PWRGD Timing Diagram CY28405 Device is not affected, VTT_PWRGD# is ignored State 3 On Page ...
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... VDDA = 2.0V S0 Power Off Figure 6. Clock Generator Power-up/Run State Diagram Document #: 38-07512 Rev VTT_PWRGD# = Low Delay >0.25mS S3 Normal VDDA = off Operation VTT_PWRGD# = toggle CY28405 S2 Sample Inputs straps Wait for 1.146ms Enable Outputs Page ...
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... Conditions 3.3V ± 5% SDATA, SCLK SDATA, SCLK V Except Pull-ups or Pull-downs 0 < V < – 200 MHz and all outputs loaded per Table 9 and Figure 7 PD# Asserted CY28405 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 +150 ° ° ...
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... See Figure 7. Measure SE – Measurement at 1.5V 45 Measurement at 1.5V 14.9955 Measurement at 1.5V 14.9955 Measurement at 2.4V 4.9500 Measurement at 0.4V 4.5500 Measured between 0.4V and 0.5 2.4V Measurement at 1.5V – Measurement at 1.5V – Measurement at 1.5V 45 Measurement at 1.5V 29.9910 Measurement at 1.5V 29.9910 Measurement at 2.4V 12.0 CY28405 Max. Unit 52.5 % 71.0 ns 10.0 ns 500 ps 300 ppm 55 % 10.003 ns 7.5023 ns 5.0015 ns 100 ps 125 ps 700 ps ...
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... Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V 125-µs period Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Conditions 3V66 Leads PCI Typical 0° 180° 0° CY28405 Min. Max. 12.0 – 0.5 2.0 – 500 – 250 45 55 20.8257 20.8340 8.994 10.486 8.794 10.386 ...
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... Output Current REF I = 6*I OH REF Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C CY28405 0. Page ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead Shrunk Small Outline Package O48 2 C system, provided that the system conforms to the I CY28405 51-85061-* Standard Specification ...
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... Document History Page Document Title: CY28405 CK409-Compliant Clock Synthesizer Document Number: 38-07512 REV. ECN NO. Issue Date ** 125354 04/15/03 *A 127159 06/16/03 *B 235894 See ECN Document #: 38-07512 Rev. *B Orig. of Change RGL New Data Sheet RGL Removed SRC functionality Modified the title to CK409-Compliant Clock Synthesizer RGL ...