CY28404 Cypress Semiconductor, CY28404 Datasheet - Page 10

• Manufacturer Part Number: CY28404
• Description: CK409-COMPLIANT CLOCK SYNTHESIZER
• Manufacturer: Cypress Semiconductor

Document #: 38-07510 Rev. *B
Byte 14: Control Register 14 (continued)
Dial-A-Frequency Programming
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * N/M.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[E:A] or SEL[4:0]. The value is
listed in Table 2.
The ratio of N and M needs to be greater than “1” [N/M> 1].
Table 6 lists set of N and M values for different frequency
output ranges.This example use a fixed value for the M-Value
Register and select the CPU output frequency by changing the
value of the N-Value Register.
Table 6. Examples of N and M Value for Different CPU
Frequency Range
Table 7. Crystal Recommendations
Frequency
100—125 24004009.32
126—166 32005345.76
167—200 48008018.65
14.31818 MHz
Ranges
Frequency
Bit
1
4
3
2
0
(Fund)
0
0
Constants
@Pup
0
0
0
Gear
Cut
AT
Reserved
Reserved
Reserved
Reserved
Pro_Freq_EN
Fixed Value
for M-Value
Loading Load Cap
Parallel
Register
48
48
48
Name
Figure 1. Crystal Capacitive Clarification
Range of N-Value
20 pF
Different CPU
Register for
Frequency
200–250
189–249
167–200
0.1 mW
(max.)
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
Programmable output frequencies enabled
0 = disabled, 1 = enabled
Drive
Shunt Cap
Crystal Recommendations
The CY28404 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28404 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
(max.)
5 pF
Motional
0.016 pF
(max.)
Description
Tolerance
50 ppm
(max.)
Stability
50 ppm
(max.)
CY28404
Page 10 of 20
(max.)
Aging
5 ppm