CY28343 Cypress Semiconductor, CY28343 Datasheet - Page 7

• Manufacturer Part Number: CY28343
• Description: Zero Delay SDR/DDR Clock Buffer
• Manufacturer: Cypress Semiconductor

Table 6. AC Parameters for SDRAM Outputs: VDD_3.3V = 2.5V ±5%, AVDD_3.3V = 3.3V ±5%, TA = 0°C to +70°C
Notes:
Differential Parameter Measurement Information
Document #: 38-07369 Rev. *A
10. The tSKEW specification is only valid for equal loading of all outputs (30 pF lump-load). Measurement are acquired at 1.5V for 3.3V signals.
11. The test load is 30 pF lump-load.
12. TR/TF are measured at 0.4V to 2.4V.
fCLK
tDCI
tLOCK
tDCO
Tr/Tf
12]
tpZL, tpZH
tpLZ, tpHZ
tCCJ
tPHASE
tSKEW
VOUT
Vx
Parameter
[10, 11,
[9]
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL Lock Time
Output Clock Duty Cycle
Output Clocks Slew Rate
Output Enable Time (all outputs)
Output Disable Time (all outputs)
Cycle-to-Cycle Jitter
Any Output to Any Output Skew
Output Voltage Swing
Output Crossing Voltage
Phase Error
C K _IN
F B IN
Description
[11]
1.25V /1.5V
[11]
t
( )
n =
[11]
1.25V /1.5 V
t
( )
VDD_3.3V = 3.3V ±5%
100 MHz, 133 MHz
@133 MHz
@133 MHz
Figure 1. Phase Error
n
1
n
N
=
N
t
Condition
( )
n
( N is large num ber o f sam ples)
(V
DD
Min
/2) – 0.2
0.4
1.1
99
45
45
V
Typ
DD
50
90
3
3
/2
1.25V
(V
t
( )
V
DD
1.2 5V
DD
n+1
Max
133
200
400
200
/2) + 0.2
1.5
1.6
55
55
5
5
– 0.4
CY28343
Page 7 of 10
MHz
Unit
ms
ps
ns
ns
ps
ps
ps
%
%
V
V