CY28343 Cypress Semiconductor, CY28343 Datasheet - Page 6

• Manufacturer Part Number: CY28343
• Description: Zero Delay SDR/DDR Clock Buffer
• Manufacturer: Cypress Semiconductor

Maximum Ratings
Maximum Input Voltage Relative to V
Maximum Input Voltage Relative to V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: .................................... 0°C to +70°C
Maximum ESD Protection:...........................................2000V
Maximum Power Supply: ................................................5.5V
DC Parameters
Table 5. AC Parameters for DDRT/C (0:5): VDD_2.5V = 2.5V ±5%, AVDD_3.3V = 3.3V ±5%, TA = 0°C to +70°C
Notes:
Document #: 38-07369 Rev. *A
5.
6.
7.
8.
9.
V
V
V
V
V
V
I
I
C
fCLK
tDCI
tDCO
tLOCK
Tr/Tf
tpZL, tpZH
tpLZ, tpHZ
tHPJ
tPHASE
tSKEW
VOUT
Vx
Parameter
OZ
DDQ
Parameter
IL
IH
IL
IL
IH
IH
in
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Unused inputs must be held high or low to prevent them from floating.
All differential output terminals are terminated with 120 /16 pF as shown in Figure 4.
Refers to the transition of non-inverting output.
Time required for the integrated PL circuit to obtain phase lock of its feed back signal to its reference signal. For Phase lock specifications for propagation delay,
skew and jitter parameters given in the switching characteristics table are not applicable.
[9]
Operating Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Maximum PLL Lock Time
Output Clocks Slew Rate
Output Enable Time
Output Disable Time
Half-Period Jitter
Phase Error
Any Output to Any Output Skew
Output Voltage Swing
Output Crossing Voltage
Input Low Voltage
Input High Voltage
CLKIN Input Low Voltage
(SDR Mode, VDD_3.3V = 3.3V)
CLKIN Input Low Voltage
(DDR Mode, VDD_2.5V = 2.5V)
CLKIN Input High Voltage
(SDR Mode, VDD_3.3V = 3.3V)
CLKIN Input High Voltage
(DDR Mode, VDD_2.5V = 2.5V)
High-Impedance Output Current
Dynamic Supply Current
Input Pin Capacitance
[6]
:
TA = 0°C to +70°C
[5]
Description
Description
[7]
[8]
[8]
[7]
(all outputs)
SS
SS
(all outputs)
[7]
: ............. V
: ............ V
[7]
SS
SS
VDD_2.5V = 2.5V ±5%
20% to 80% of VDD_2.5V
@100 MHz and 133 MHz
@133 MHz
– 0.5V
+ 0.7V
SDATA, SCLK
CLKIN, FBIN_SDR
CLKIN, FBIN_DDR
CLKIN, FBIN_SDR
CLKIN, FBIN_DDR
V
V
F
O
O
O
Condition
= 133 MHz
= GND or
= VDD
Condition
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
range:
V
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
< (V
in
or V
(V
out
DD
Min.
Min.
) < V
–0.3
–0.3
/2) – 0.2
–10
1.0
1.1
2.2
2.0
1.7
99
45
47
SS
in
or V
DD
and V
DD
).
out
Typ.
V
235
Typ.
DD
4
50
90
3
3
should be constrained to the
/2
(V
V
V
V
DD
DD
Max.
DD
DD
300
Max.
1.0
0.8
0.7
10
170
125
200
150
/2) + 0.2
1.5
2.3
+ 0.3
+ 0.3
55
53
5
5
– 0.4
CY28343
Page 6 of 10
Unit
mA
ma
pF
MHz
V/ns
Unit
V
V
V
V
V
V
ms
ns
ns
ps
ps
ps
%
%
V
V