CY28343 Cypress Semiconductor, CY28343 Datasheet - Page 2

• Manufacturer Part Number: CY28343
• Description: Zero Delay SDR/DDR Clock Buffer
• Manufacturer: Cypress Semiconductor

Pin Description
Notes:
Power Management
The individual output enable/disable control of the CY28343
allows the user to implement unique power management
schemes into the design. Outputs are in LOW state when dis-
abled through the two-line interface as individual bits are set
LOW in Byte0 to Byte2 registers. The feedback output
FBOUT_DDR and FBOUT_SDR cannot be disabled via
two-line serial bus.
Document #: 38-07369 Rev. *A
2.
3.
10
47
23
30,32,36,38
42,44
29,31,35,37
41,43
2-5,8,9
15-18,21
46
22
48
26
25
1,7,14,20,27
33,39,45
6,13,19,24,28
,34,40
PU = internal pull-up PD = internal pull-down.
A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Pin
CLKIN
FBIN_DDR
FBIN_SDR
DDRT(0:5)
DDRC(0:5)
SDRAM(0:12)
FBOUT_DDR
FBOUT_SDR
SELDDR_SDR#
SCLK
SDATA
VDD_3.3V
VDD_2.5V
VSS
[2, 3]
Name
PD
PD
PD
PU
PU
I/O
I/O
O
O
O
O
O
I
I
I
I
I
Clock Input. Reference the PLL
Feedback Clock Output. Connect to FBOUT_DDR for accessing the PLL.
See Function Table on page 1
Feedback Clock Input. Connect to FBOUT_SDR for accessing the PLL. See
Function Table on page 1
Clock Outputs. True copies of the CLKIN input
Clock Outputs. Complementary copies of the CLKIN input
Clock Outputs. True copies of the CLKIN input
Feedback Clock Output. Connect to FBIN_DDR for normal operation. A true
copy of the CLKIN input. The delay of the PCB trace RC at this output will
control Input Reference/DDR Output Clocks phase relationships.
Feedback Clock Output. Connect to FBIN_SDR for normal operation. A true
copy of the CLKIN input. The delay of the PCB trace RC at this output will
control Input Reference/ SDR Output Clocks phase relationships.
SDR or DDR Select Pin. See Function Table on page 1
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to enable/disable
individual outputs. This provides flexibility in power management.
3.3V power supply for SDR outputs and two line serial Interface
2.5V power supply for DDR outputs
Common Ground
Zero Delay Buffer
When used as a
in a nested clock tree application. For these applications the
CY28343 offers single-end input as a PLL reference. The
CY28343 then can lock onto the reference and translate with
near zero to low-skew outputs. For normal operation, the ex-
ternal feedback input, FBIN_DDR and FBIN_SDR, are con-
nected
FBOUT_SDR. By connecting the feedback output to the feed-
back input the propagation delay through the device is elimi-
nated. The PLL works to align the output edge with the input
reference edge thus producing a near zero delay. The refer-
ence frequency affects the static phase offset of the PLL and
thus the relative delay between the inputs and outputs.
to
the
Description
ZERO
feedback
delay buffer the CY28343 will likely be
output,
FBOUT_DDR
CY28343
Page 2 of 10
and