CY28324 Cypress Semiconductor, CY28324 Datasheet - Page 10

• Manufacturer Part Number: CY28324
• Description: FTG for Intel Pentium 4 CPU and Chipsets
• Manufacturer: Cypress Semiconductor

Data Byte 8
Data Byte 9
Document #: 38-07002 Rev. *A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Pin#
Pin#
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Reserved
Reserved
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
WD_PRE_SCALER
48MHz_DRV
PCI_DRV
3V66_DRV
RST_EN_WD
RST_EN_FC
WD_TO_STATUS
WD_EN
Reserved
Name
Name
PRELIMINARY
Reserved
Reserved
The scale of the timer is determine by the prescaler.
The timer can support a value of 150 ms to 4.8 sec when
the prescalar is set to 150 ms. If the prescaler is set to 2.5
sec, it can support a value from 2.5 sec. to 80 sec.
When the Watchdog Timer reaches “0,” it will set the
WD_TO_STATUS bit and generate Reset if RST_EN_WD
is enabled.
1 = 2.5 sec
48MHz & 24_48MHz clock output drive strength
0 = Normal
1 = High Drive
(Recommend to set to high drive if this output is being
used to drive both USB and SIO devices in Intel®
Brookdale - G platforms)
PCI clock output drive strength
0 = Normal
1 = High Drive
3V66 clock output drive strength
0 = Normal
1 = High Drive
a Watchdog Timer time-out occurs.
0 = Disabled
1 = Enabled
frequency change occurs.
0 = Disabled
1 = Enabled
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = Time-out occurred (READ); Clear WD_TO_STATUS
(WRITE)
1 = Enable Watchdog Timer. It will start counting down
after a frequency change occurs.
Note: CY28324 will generate system reset, reload a re-
covery frequency, and lock itself into a recovery frequency
mode after a Watchdog Timer time-out occurs. Under re-
covery frequency mode, CY28324 will not respond to any
attempt to change output frequency via the SMBus control
bytes. System software can unlock CY28324 from its re-
covery frequency mode by clearing the WD_EN bit.
Reserved
These bits store the time-out value of the Watchdog Timer.
0 = 150 ms
This bit will enable the generation of a Reset pulse when
This bit will enable the generation of a Reset pulse after a
0 = Stop and reload Watchdog Timer
Pin Description
Pin Description
CY28324
Page 10 of 23
Power-On
Power-On
Default
Default
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0