CY28324 Cypress Semiconductor, CY28324 Datasheet
CY28324
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CY28324 Summary of contents
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... VTT_PWRGD# GND_48MHz *FS0/48MHz *FS1/24_48MHz VDD_48MHz VDD_48MHz 48MHz Note: 24_48MHz 1. Signals marked with ‘*’ have internal pull-up resistor. 2 RST# • 3901 North First Street • CY28324 ® 4 CPU and Chipsets 3V66 PCI REF 48M SSOP- REF0/MULTSEL0* 2 ...
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... This pin also serves as a power-on strap option to determine device op- erating frequency as described in the Frequency Selection Table. I/O Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI out- put. This pin also serves as a power-on strap option to determine device op- erating frequency as described in the Frequency Selection Table. CY28324 Pin Description Page ...
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... MODE and MULTSEL0:1 inputs are valid and sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. P 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. CY28324 Pin Description Page ...
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... Document #: 38-07002 Rev. *A PRELIMINARY Pin Type G Ground Connection: Connect all ground pins to the common system ground plane. P 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. G Analog Ground Connection: Ground for core logic, PLL circuitry. CY28324 Pin Description Page ...
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... IREF = 5. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2.32 mA CY28324 Output Current 4*IREF 1. 4*IREF 1. 5*IREF 1.25V @ 5*IREF 1. 6*IREF 1. ...
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... CY28324 Block Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – ...
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... SW Frequency selection bits. See Table 4. (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) CY28324 Byte Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset ...
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... Ioh IREF 01 = Ioh IREF 10 = Ioh IREF 11 = Ioh IREF Reserved Reserved Reserved 0 = Not free running 1 = Free running; not affected by CPU_STOP Not free running 1 = Free running; not affected by CPU_STOP# CY28324 Pin Description Pin Description Pin Description Power-On Default ...
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... Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28324 Pin Description Pin Description Pin Description Power-On Default ...
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... Watchdog Timer time-out occurs. Under re- covery frequency mode, CY28324 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28324 from its re- covery frequency mode by clearing the WD_EN bit. Reserved CY28324 ...
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... ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL From latched FS[4: From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] CY28324 Pin Description Pin Description Pin Description Power-On Default 0 0 ...
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... CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Reserved Reserved Reserved Reserved CY28324 Pin Description Pin Description Pin Description Pin Description Power-On Default 0 ...
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... Reserved. Write with “1” Reserved. Write with “1” Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28324 Pin Description Pin Description Pin Description Power-On Default Power-On Default ...
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... CY28324 PLL Gear Constants 3V66 PCI 68.0 34.0 48.00741 70.0 35.0 48.00741 72.0 36.0 48.00741 74.0 37.0 48.00741 76.0 38.0 48.00741 78.0 39.0 48.00741 80.0 40.0 48.00741 82.0 41.0 48.00741 63.0 31.5 48.00741 65.0 32.5 48.00741 68.0 34.0 48.00741 70.0 35 ...
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... Watchdog Timer before they attempt to make a frequency change. If the system hangs and a Watchdog Timer time-out occurs, a system reset will be gen- erated and a recovery frequency will be activated. All the related registers are summarized in the following table. Description CY28324 Page ...
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... M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for M-Value Register 93 45 CY28324 Range of N-Value Register for Different CPU Frequency 97–255 127–245 Page ...
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... PCI 0 < V < < V < For I =6*IRef Configuration OH REF, 48 MHz, 3VMREF 3V66, 3VMREF, PCI REF, 3VMREF, 48 MHz 3V66, PCI, 3VMREF Three-state CPU VDD_CORE/VDDQ3 = 3.465V CY28324 Min. Max. 3.135 3.465 22 14.318 14.318 Min. Max. Unit /2 2 – ...
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... Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V Where rising edge and intersecting falling edge CY28324 Min. Max 175 700 oh 0.5 2.0 1.0 4.0 175 700 oh ...
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... Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t 5 PCI-PCI Clock Skew PCI PCI t 6 Document #: 38-07002 Rev. *A PRELIMINARY CY28324 Page ...
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... CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Ordering Information Package Ordering Code Name CY28324PVC O48 Document #: 38-07002 Rev. *A PRELIMINARY Package Type 48-pin Small Shrunk Outline Package (SSOP) CY28324 Operating Range Commercial Page ...
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... Cermaic Caps C3 = 10– VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 CY28324 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead Shrunk Small Outline Package O48 CY28324 51-85061-B Page ...
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... Document Title: CY28324 FTG For Intel Document Number: 38-07002 Issue REV. ECN NO. Date ** 105839 03/30/01 *A 110865 11/15/01 Document #: 38-07002 Rev. *A PRELIMINARY ® ® Pentium 4 CPU and Chipsets Orig. of Change Description of Change IKA New Spec. IKA Revised 2nd bullet on p.1: Intel 850, Brookdale (845) Added note on p.3 and p.9 regarding Brookdale platform ...