AN2074 Freescale Semiconductor / Motorola, AN2074 Datasheet - Page 6

• Manufacturer Part Number: AN2074
• Description: DSP56300 JTAG Examples
• Manufacturer: Freescale Semiconductor / Motorola

6
Instruction Register
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EXTEST (B[3–0] = 0000). This instruction is required by IEEE Standard 1149.1. EXTEST places
the DSP into an external test mode and connects the BSR between
drives the external outputs through the output boundary cells beginning with the values inserted
by the previous SAMPLE/PRELOAD instruction and receives external test data via the boundary
inputs. Sets of data can be shifted through the BSR to drive the DSP outputs at various levels and
to sample the concurrent DSP inputs.
SAMPLE/PRELOAD (B[3–0] = 0001). This instruction is required by IEEE Standard 1149.1.
SAMPLE/PRELOAD allows the DSP to remain in its functional mode and connects the BSR
between
leaving the DSP. This instruction can also preload test data into the BSR before loading and
executing an EXTEST or CLAMP instruction.
IDCODE (B[3–0] = 0010). This optional instruction is specified in IEEE Standard 1149.1.
IDCODE allows the DSP to remain in its functional mode and connects the ID Register between
TDI
component from the TAP. This is the default value loaded into the IR at reset.
HIGHZ (B[3–0] = 0100). This optional instruction is specified in IEEE Standard 1149.1. HIGHZ
sets all DSP outputs to a high impedance state and connects the Bypass Register between
TDO
without affecting the condition of the DSP outputs.
CLAMP (B[3–0] = 0101). This optional instruction is specified in IEEE Standard 1149.1.
CLAMP sets the outputs of the DSP to logic levels determined by the contents of the BSR,
typically preset by using the SAMPLE/PRELOAD instruction, and connects the Bypass Register
between
from
ENABLE_ONCE (B[3–0] = 0110). This instruction is not specified in IEEE Standard 1149.1 but
is defined as part of the DSP56300 architecture to provide added debug functionality.
ENABLE_ONCE allows you to perform system debug functions and connects the OnCE Control
Register (OCR) between
OnCE registers depending on which OnCE instruction is executed.
DEBUG_REQUEST (B[3–0] = 0111). This instruction is not specified in IEEE Standard 1149.1
but is defined as part of the DSP56300 architecture to provide added debug functionality.
DEBUG_REQUEST generates a debug request signal to the DSP56300 core. When this
instruction is decoded, the
core signals that it has entered Debug mode (indicated by a value of 1101 being shifted out from
the Instruction Register). The external JTAG controller must continue to shift in the
DEBUG_REQUEST instruction while polling the status bits that are shifted out until the system
enters Debug mode. After the acknowledgment of Debug mode is received, the external JTAG
controller must issue the ENABLE_ONCE instruction to allow the user to perform system debug
functions.
BYPASS (B[3–0] = 1111). This instruction is required by IEEE Standard 1149.1. BYPASS allows
the DSP to remain in its functional mode and connects the Bypass Register between
It allows serial data to pass through the DSP from
operation.
and
. While this instruction executes, data shifts through the Bypass Register from
TDI
TDO
TDI
TDI
to
TDO
and
and
. It allows the user to read the manufacturer, part number, and version of a
TDO
TDO
without affecting the condition of the DSP outputs.
Freescale Semiconductor, Inc.
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. The BSR can be used to take a snapshot sample of the functional data
. While this instruction executes, data shifts through the Bypass Register
TDI
TDI
DSP56300 JTAG Examples
and
and
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TDO
TDO
. The OCR writes data to and reads data from the other
pins remain connected to the Instruction Register until the
TDI
to
TDO
without affecting the DSP
TDI
and
TDO
. The BSR content
TDI
TDI
to
and
TDI
TDO
TDO
and
.