AN2074 Freescale Semiconductor / Motorola, AN2074 Datasheet

AN2074

Manufacturer Part Number

AN2074

Description

DSP56300 JTAG Examples

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

1.AN2074.pdf (36 pages)

Current page: 1 of 36
Download datasheet (394Kb)

NDI

TDI

MOTOROLA

Semiconductor Products Sector Application Note

DSP56300 JTAG Examples

Barbara Johnson

IEEE Specification 1149.1 defines a recommended test

architecture with a standard serial interface to permit snapshot

sampling of individual pin signals without requiring a direct

electrical contact (such as that done in a bed-of-nails test

environment). The boundary-scan technique can also be used to

drive specific output signals. This application note gives an

overview of the boundary scan architecture and discusses the

specific implementation of the Test Access Port (TAP) in the

Motorola DSP56300 family of digital signal processors. Example

code is provided to illustrate how to use these test features.

The test architecture uses a boundary-scan cell (BSC) connected

between every I/O pin and the internal device circuitry. The BSCs

interconnect to form a Boundary Scan Register (BSR). The BSR

is one of several data registers that make up the test structure.

When selected by the appropriate TAP controller instruction, the

BSR becomes a serial scan path between a test data input (

and a test data output (

input signals pass freely through the BSCs from the normal data

inputs (NDIs) to the internal circuitry. Similarly, the output

signals pass freely through the BSCs from the internal circuitry to

the normal data outputs (NDOs). However, when the system

enters boundary-test mode, external input test stimuli can be

applied through the NDIs, sampled by the BSCs, and shifted out

to verify a proper electrical connection. Similarly, test values can

be shifted in and applied to the BSCs connected to the NDOs, and

the electrical outputs can be observed through other devices (such

as a logic analyzer or another DSP) to verify a proper electrical

connection for the outputs. Figure 1 shows the BSC block

diagram.

BSC

Figure 1. Boundary-Scan Cells

TDO

and Peripherals

Freescale Semiconductor, Inc.

DSP Core

For More Information On This Product,

) pin. During normal operation, the

Go to: www.freescale.com

BSC

TDI

TDO

NDO

)

1.1

1.2

1.3

1.4

1.5

1.6

1.7

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

3.1

3.2

3.2.1 JTAG_RTI Subroutine .................. 18

3.2.2 JTAG_EXECUTE Subroutine....... 19

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Test Access Port .......................3

JTAG Pins........................................ 3

TAP Controller ................................ 3

Instruction Register.......................... 5

Bypass Register ............................... 7

ID Register....................................... 7

Boundary-Scan Register .................. 7

TAP Signals Example.................... 10

Boundary-Scan Description

Language.................................11

Entity Description.......................... 11

Generic Parameter ......................... 11

Logical Port ................................... 12

Pin Mapping .................................. 12

Scan Port Identification ................. 13

Instruction Register........................ 13

ID Code Register ........................... 14

Boundary Register ......................... 14

Programming Examples ........17

Test Setup ...................................... 17

Entering the Run-Test/Idle State ... 18

BYPASS Example......................... 19

IDCODE Example......................... 21

HIGHZ Example............................ 24

SAMPLE/PRELOAD Example..... 25

CLAMP Example .......................... 29

EXTEST Example ......................... 30

Daisy Chain Example .................... 31

Contents

Order Number: AN2074/D

Rev. 0, 11/2000

Related parts for AN2074

AN2074 Summary of contents

Page 1

... TDI ) 3.2.1 JTAG_RTI Subroutine .................. 18 3.2.2 JTAG_EXECUTE Subroutine....... 19 3.3 3.4 3.5 3.6 3.7 3.8 3.9 NDO BSC TDO Go to: www.freescale.com Order Number: AN2074/D Rev. 0, 11/2000 Contents Test Access Port .......................3 JTAG Pins........................................ 3 TAP Controller ................................ 3 Instruction Register.......................... 5 Bypass Register ............................... 7 ID Register....................................... 7 Boundary-Scan Register .................. 7 TAP Signals Example.................... 10 Boundary-Scan Description Language.................................11 Entity Description.......................... 11 Generic Parameter ......................... 11 Logical Port ...

Page 2

Freescale Semiconductor, Inc. As noted above, the IEEE 1149.1 test structures include several data registers. The architecture also requires an instruction register. All of the registers are accessed serially through the TAP, and, when selected, connect between the TDI controller, ...

Page 3

Freescale Semiconductor, Inc. 1 Test Access Port The TAP is the external interface for the internal test circuitry specified by IEEE 1149.1. It consists of the following: • Five dedicated signal pins • 16-state TAP controller • Instruction Register • ...

Page 4

Freescale Semiconductor, Inc. TAP Controller TMS=1 Test-Logic-Reset TMS=0 TMS=0 TMS=1 Run-Test/Idle TMS=0 Figure 3. TAP Controller State Machine At power up or during normal operation of the DSP, This immediately places the TAP in the Test-Logic-Reset state. The TAP can ...

Page 5

Freescale Semiconductor, Inc. After reset, you can read the Device ID Register (default). To perform any other action, you must move the TAP to the Instruction Register scan cycle to select an appropriate data register. For either type of scan ...

Page 6

Freescale Semiconductor, Inc. Instruction Register • EXTEST (B[3–0] = 0000). This instruction is required by IEEE Standard 1149.1. EXTEST places the DSP into an external test mode and connects the BSR between drives the external outputs through the output boundary ...

Page 7

Freescale Semiconductor, Inc. 1.4 Bypass Register The Bypass Register provides a single-bit scan path between when a device other than the DSP56300 core-based device becomes the device under test. When the Bypass Register is selected by the current instruction, the ...

Page 8

Freescale Semiconductor, Inc. Boundary-Scan Register Table 3. DSP56307 Boundary-Scan Register Bit Definitions (Continued) Bit Pin Name Pin Type Number 4 D23 Input/Output 5 D22 Input/Output 6 D21 Input/Output 7 D20 Input/Output 8 D19 Input/Output 9 D18 Input/Output 10 D17 Input/Output ...

Page 9

Freescale Semiconductor, Inc. Table 3. DSP56307 Boundary-Scan Register Bit Definitions (Continued) Bit Pin Name Pin Type Number 39 A9 Tri-State 40 A8 Tri-State 41 A7 Tri-State 42 A6 Tri-State 43 A[8–0] — Tri-State 45 A4 Tri-State 46 A3 ...

Page 10

Freescale Semiconductor, Inc. TAP Signals Example 1.7 TAP Signals Example Table 4 describes the signals used in the TAP example and Figure 4 shows a typical sequence of signal events for loading the BYPASS instruction 1111 into the Instruction Register. ...

Page 11

Freescale Semiconductor, Inc TCK TRST TMS TDI TDO 2 Boundary-Scan Description Language Boundary-Scan Description Language (BSDL) describes how IEEE 1149.1 is implemented in a device and how the device operates. A BSDL description for a device consists ...

Page 12

Freescale Semiconductor, Inc. Pin Mapping 2.3 Logical Port The logical port description gives logical names to the I/O pins and specifies whether the signals are input, output, bidirectional, or linkage (power supply). Example 3 shows the DSP56307 logical port description. ...

Page 13

Freescale Semiconductor, Inc. "SC00: F3, " & "QVCCH: (F12, H1, M7), " & "SCK1: G1, " & "SCLK: G2, " & "TXD: G3, " & "SCK0: H3, " & "AVCC: (H12, K12, L12), " & "HACK: J1, " & "HRW: ...

Page 14

Freescale Semiconductor, Inc. Boundary Register instruction opcode definitions. It also defines that in the Capture-IR state, the parallel inputs to the instruction shift register are loaded with 01 in the least significant bits. Example 6. Instruction Register Description attribute INSTRUCTION_LENGTH ...

Page 15

Freescale Semiconductor, Inc. "16 (BC_6, D(12), bidir, X, 13, 1, Z)," & "17 (BC_6, D(11), bidir, X, 26, 1, Z)," & "18 (BC_6, D(10), bidir, X, 26, 1, Z)," & "19 (BC_6, D(9), bidir, X, 26, 1, Z)," & -- ...

Page 16

Freescale Semiconductor, Inc. Boundary Register "76 (BC_6, HAD(1), bidir, X, 75, 1, Z)," & "77 (BC_1, *, control, 1)," & "78 (BC_6, HAD(2), bidir, X, 77, 1, Z)," & "79 (BC_1, *, control, 1)," & -- num cell port func ...

Page 17

... Target DSP: DSP56307EVM • TAP bus master: DSP56303EVM • PC with Motorola DSP56300 software development tools • Logic analyzer The software that exercises the TAP is downloaded from the PC to the DSP56307 via the JTAG/OnCE port. The DSP56303 acts as an external bus master by controlling the signals to the DSP56307. The logic analyzer examines the relative timing of the signals ...

Page 18

Freescale Semiconductor, Inc. Entering the Run-Test/Idle State 3.2 Entering the Run-Test/Idle State The TAP controller must be initialized into the Test-Logic-Reset state to keep the test logic transparent to the DSP56300 system logic. This operation is done by performing one ...

Page 19

Freescale Semiconductor, Inc. 3.2.2 JTAG_EXECUTE Subroutine The JTAG_EXECUTE subroutine performs the operations necessary to emulate the JTAG/OnCE operation. When the JTAG_RTI sends an 8-bit item of data, the JTAG_EXECUTE first determines if bit 2 is set to indicate that TDO ...

Page 20

Freescale Semiconductor, Inc. BYPASS Example , data shifted out on is the same as the data shifted in on TDO TDO Notice that when the least significant bit of data is shifted in, the output data is undefined. The least ...

Page 21

Freescale Semiconductor, Inc Shift DR - TDI Shift DR - TDI Shift DR - TDI Shift DR - TDI=0 dc ...

Page 22

Freescale Semiconductor, Inc. IDCODE Example x:JTAG_OUT The DSP56307 ID Register contains $0180701D. Other DSP56300 derivatives change bits 16–12. Table 9. DSP56307 IDCODE Output Description Bit Description 31–28 Version Information 27–22 Design Center Number 21–17 Core Number 16–12 Chip Derivative Number ...

Page 23

Freescale Semiconductor, Inc Shift Shift DR - msb of data out dc $ Shift DR - lsb of data out dc $ Shift ...

Page 24

Freescale Semiconductor, Inc. HIGHZ Example TDI_CLR bclr #TDI_BIT,x:M_PDRD cont2 bset #TCK_BIT,x:M_PDRD rep #3 nop bclr #TCK_BIT,x:M_PDRD brclr #COUNT24,x:JTAG_INSTR,not24bits move b1,x:(r1)- clr b not24bits bra >JTAG_EXECUTE done lsr #16,b nop move b1,x:(r1)- clr b rts 3.5 HIGHZ Example The HIGHZ example ...

Page 25

Freescale Semiconductor, Inc Update Select Capture Shift Shift DR - TDI=0 ...

Page 26

Freescale Semiconductor, Inc. SAMPLE/PRELOAD Example data reflects the sampled data on the DSP pins. Output data is stored in six memory locations x:JTAG_OUT..x:JTAG_OUT+5. The most significant word is stored in x:JTAG_OUT and the least significant word is stored in x:JTAG_OUT+5. ...

Page 27

Freescale Semiconductor, Inc Shift DR - lsb of data outD12 dc $ Shift Shift Shift ...

Page 28

Freescale Semiconductor, Inc. SAMPLE/PRELOAD Example dc $ Shift Shift Shift Shift DR - msb of data outctrl HAD3 dc ...

Page 29

Freescale Semiconductor, Inc Shift Shift Shift Shift Shift DR dc $04 ...

Page 30

Freescale Semiconductor, Inc. EXTEST Example org x: JTAG_CLAMP_SEQ Select Select Capture Shift ...

Page 31

Freescale Semiconductor, Inc. org x: JTAG_EXTEST_SEQ Select Select Capture Shift Shift ...

Page 32

Freescale Semiconductor, Inc. Daisy Chain Example Host x:JTAG_OUT The DSP56303 ID Register contains $1180301D. Table 16. DSP56307 IDCODE Output Description Bit Description 31–28 Version Information 27–22 Design Center Number 21–17 Core Number 16–12 Chip Derivative Number 11–1 Manufacturer Identity 0 ...

Page 33

Freescale Semiconductor, Inc Shift Shift Shift Shift Shift DR dc $84 ...

Page 34

Freescale Semiconductor, Inc. Daisy Chain Example NOTES: 34 For More Information On This Product, DSP56300 JTAG Examples Go to: www.freescale.com ...

Page 35

Freescale Semiconductor, Inc. NOTES: For More Information On This Product, DSP56300 JTAG Examples Go to: www.freescale.com Daisy Chain Example 35 ...

Page 36

... Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 Go to: www.freescale.com Home Page http://www.mot.com/SPS/DSP DSP Helpline http://www.motorola-dsp.com/contact email: dsphelp@dsp.sps.mot.com AN2074/D ...

Related keywords

AN2074 datasheet
AN2074 data sheet
AN2074 pdf datasheet
AN2074 component
AN2074 part
AN2074 distributor
AN2074 RoHS
AN2074 datasheet download