AN2074 Freescale Semiconductor / Motorola, AN2074 Datasheet - Page 5

• Manufacturer Part Number: AN2074
• Description: DSP56300 JTAG Examples
• Manufacturer: Freescale Semiconductor / Motorola

1.3 Instruction Register
After reset, you can read the Device ID Register (default). To perform any other action, you must move the
TAP to the Instruction Register scan cycle to select an appropriate data register. For either type of scan
cycle (data register or instruction register), the first action in the scan cycle is a capture operation. The
Capture-DR state enables the data register indicated by the current Instruction Register contents. The
Capture-IR state enables access to the Instruction Register.
From the Capture state, the TAP transitions either to the Shift or to the Exit1 state. The Shift state allows
test data or a new instruction to be shifted in or status information to be shifted out for inspection.
Following the Shift state, the TAP either returns to the Run-Test/Idle state, via the Exit1 and Update states,
or enters the Pause state, via Exit1. The Pause state allows data shifting through either the selected data
register or Instruction Register to be temporarily suspended while a required operation is performed. From
the Pause state, shifting can resume by re-entering the Shift state via the Exit2 state, or it can be terminated
by entering the Run-Test/Idle state via the Exit2 and Update states.
The Instruction Register (IR) is a required register specified in IEEE Standard 1149.1 that must be at least
1 bit long. The DSP56300 family implements a 4-bit IR that decodes the unique instructions shown in
Table 1. As shown in the table, bit combinations that are not used select the Bypass Register by default as
required by the standard. The IR consists of a shift register with four parallel outputs. Data transfers from
the shift register to the parallel outputs during the Update-IR TAP controller state. During a Shift-IR
loading sequence, data can be clocked through the Instruction Register out of
be passed to any subsequent devices in the JTAG daisy-chain.
During the Capture-IR state, the parallel inputs to the instruction shift register are loaded with 01 in the
least significant bits as required by IEEE Standard 1149.1. The two most significant bits are loaded with
the values of the core status bits OS[1–0] from the OnCE controller. See the “On-Chip Emulation Module”
section of the DSP56300 Family Manual for a description of the status bits. Table 1 summarizes the
Instruction Register encodings. A description of the valid instructions follows the table.
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Freescale Semiconductor, Inc.
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
For More Information On This Product,
Table 1. DSP56300 JTAG Instructions
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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DSP56300 JTAG Examples
EXTEST
SAMPLE/PRELOAD
IDCODE
Not assigned
HIGHZ
CLAMP
ENABLE_ONCE
DEBUG_REQUEST
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
BYPASS
Instruction
Boundary-Scan Register
Boundary-Scan Register
ID Register
Bypass Register
Bypass Register
Bypass Register
OnCE Register
OnCE Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Register Selected
TDO
to allow instructions to
Instruction Register
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