IDT72V82L20PA IDT, Integrated Device Technology Inc, IDT72V82L20PA Datasheet - Page 4

• Manufacturer Part Number: IDT72V82L20PA
• Description: IC FIFO ASYNCH 1KX9 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V82L20PA

• Function: Asynchronous
• Memory Size: 9K (1K x 9)
• Data Rate: 33MHz
• Access Time: 20ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Configuration: Dual
• Density: 18Kb
• Access Time (max): 20ns
• Word Size: 9b
• Organization: 1Kx9x2
• Sync/async: Asynchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TSSOP
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V82L20PA

SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
CONTROLS:
RESET ( RS )
During reset, both internal read and write pointers are set to the first location.
A reset is required after power up before a write operation can take place. Both
the Read Enable ( R ) and Write Enable ( W ) inputs must be in the high
state during the window shown in Figure 2, (i.e., t
edge of RS ) and should not change until t
RS. Half-Full Flag ( HF ) will be reset to high after Reset ( RS ).
WRITE ENABLE ( W )
is not set. Data set-up and hold times must be adhered to with respect to the rising
edge of the Write Enable (W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
operation, the Half-Full Flag (HF) will be set to low and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by the rising edge of the read operation.
operations. Upon the completion of a valid read operation, the Full Flag (FF)
will go high after t
internal write pointer is blocked from W, so external changes in W will not affect
the FIFO when it is full.
READ ENABLE ( R )
the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,
independent of any ongoing write operations. After Read Enable (R) goes high,
the Data Outputs (Q
next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go low, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (EF) will go high
after t
read pointer is blocked from R so external changes in R will not affect the FIFO
when it is empty.
FIRST LOAD/RETRANSMIT ( FL/RT )
grounded to indicate that it is the first loaded (see Operating Modes). In the
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
Data inputs for 9-bit wide data.
Reset is accomplished whenever the Reset (RS) input is taken to a low state.
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
After half of the memory is filled and at the falling edge of the next write
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write
A read cycle is initiated on the falling edge of the Read Enable (R) provided
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
WEF
and a valid Read can then begin. When the FIFO is empty, the internal
0
– D
RFF
8
)
0
, allowing a valid write to begin. When the FIFO is full, the
– Q
8
) will return to a high impedance condition until the
RSR
after the rising edge of
RSS
before the rising
4
Single Device Mode, this pin acts as the retransmit input. The Single Device
Mode is initiated by grounding the Expansion In (XI).
data when the Retransmit Enable control (RT) input is pulsed low. A retransmit
operation will set the internal read pointer to the first location and will not affect
the write pointer. Read Enable (R) and Write Enable (W) must be in the high
state during retransmit for the IDT72V81/72V82/72V83/72V84/72V85 respec-
tively. This feature is useful when less than 512/1,024/2,048/4,096/8,192 writes
are performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
the relative locations of the read and write pointers.
EXPANSION IN ( XI )
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG ( FF )
pointer is one location less than the read pointer, indicating that the device is full.
If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low
after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes
for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the
IDT72V85.
EMPTY FLAG ( EF )
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF )
sion In (XI) is grounded, this output acts as an indication of a half-full memory.
operation, the Half-Full Flag (HF) will be set low and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by using rising edge of the read operation.
Out (XO) of the previous device in the Daisy Chain by providing a pulse to the
next device when the previous device reaches the last location of memory.
DATA OUTPUTS ( Q
condition whenever Read (R) is in a high state.
The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit
This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate
The Full Flag (FF) will go low, inhibiting further write operation, when the write
The Empty Flag (EF) will go low, inhibiting further read operations, when
This is a dual-purpose output. In the single device mode, when Expan-
After half of the memory is filled and at the falling edge of the next write
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Data outputs for 9-bit wide data. This data is in a high impedance
0
– Q
8
)
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 5, 2009