HT48CA3 Holtek Semiconductor Inc, HT48CA3 Datasheet - Page 12

• Manufacturer Part Number: HT48CA3
• Description: 8-Bit Remote Type MCU
• Manufacturer: Holtek Semiconductor Inc

Timer/Event Counter
Two timer/event counters are implemented in the de-
vice. The Timer/Event Counter 0 contains an 8-bit pro-
grammable count-up counter and the clock may come
from an external source or the system clock. The
Timer/Event Counter 1 contains an 16-bit programma-
ble count-up counter and the clock may come from an
external source or the system clock divided by 4.
Of the two timer/event counters, using external clock in-
put allows the user to count external events, measure
time internals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
Only the Timer/Event Counter 0 can generate PFD sig-
nal by using external or internal clock, and PFD fre-
quency is determine by the equation f
There are 2 registers related to Timer/Event Counter 0;
TMR0(0DH), TMR0C(0EH). In Timer/Event Counter 0
counting mode (TON=1), writing TMR0 will only put the
written data to preload register (8 bits). The Timer/Event
Counter 0 preload register is changed by each writing
TMR0 operations. Reading TMR0 will also latch the
TMR0 to the destination. The TMR0C is the Timer/Event
Counter 0 control register, which defines the operating
mode, counting enable or disable and active edge.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0) pin. The timer mode functions as a normal timer
with the clock source coming from the f
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR0). The counting is based on the f
In the event count or timer mode, once the Timer/Event
Counter 0 starts counting, it will count from the current
contents in the Timer/Event Counter 0 to FFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 0 preload register and generates
the corresponding interrupt request flag (T0F; bit 5 of
INTC) at the same time.
In pulse width measurement mode with the TON and TE
bits are equal to one, once the TMR0 has received a
transition from low to high (or high to low if the TE bit is 0)
it will start counting until the TMR0 returns to the original
level and reset the TON. The measured result will re-
main in the Timer/Event Counter 0 even if the activated
transition occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transition pulse. Note that, in this operat-
ing mode, the Timer/Event Counter 0 starts counting not
according to the logic level but according to the transi-
tion edges. In the case of counter overflows, the counter
0 is reloaded from the Timer/Event Counter 0 preload
Rev. 1.40
INT
INT
/[2 (256-N)].
INT
clock.
clock. The
12
register and issues the interrupt request just like the
other two modes.
To enable the counting operation, the timer ON bit (TON;
bit 4 of TMR0C) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is complete. But in the
other two modes the TON can only be reset by instruc-
tions. The overflow of the Timer/Event Counter 0 is one
of the wake-up sources. No matter what the operation
mode is, writing a 0 to ET0I can disabled the corre-
sponding interrupt service.
In the case of Timer/Event Counter 0 Off condition, writ-
ing data to the Timer/Event Counter 0 preload register
will also load the data to Timer/Event Counter 0. But if
the Timer/Event Counter 0 is turned On, data written to
the Timer/Event Counter 0 will only be kept in the
Timer/Event Counter 0 preload register. The
Timer/Event Counter 0 will still operate until the overflow
occurs (a Timer/Event Counter 0 reloading will occur at
the same time).
When the Timer/Event Counter 0 (reading TMR0) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The bit 0~2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 0. The definitions are as shown.
(TMR0C)
PSC0~
PSC2
TE
TON
TM0
TM1
Label
Bits
0~2
3
4
5
6
7
To define the prescaler stages,
PSC2, PSC1, PSC0=
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
To define the TMR0 active edge of
Timer/Event Counter 0
(0=active on low to high;
1=active on high to low)
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
Unused bit, read as 0
To define the operating mode
01=Event count mode (external
clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C register
INT
INT
INT
INT
INT
INT
INT
INT
=f
=f
=f
=f
=f
=f
=f
=f
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
Function
/2
/4
/8
/16
/32
/64
/128
/256
HT48CA3
July 16, 2003