HT48CA3 Holtek Semiconductor Inc, HT48CA3 Datasheet - Page 10

• Manufacturer Part Number: HT48CA3
• Description: 8-Bit Remote Type MCU
• Manufacturer: Holtek Semiconductor Inc

in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If it awakens from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place. If an interrupt request flag is
set to 1 before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PD and TO flags, the
program can distinguish between different chip resets .
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Rev. 1.40
TO
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
0
u
0
1
1
PD
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
RESET Conditions
SYS
(system clock
10
The functional unit chip reset status are shown below.
PC
Interrupt
Prescaler
WDT
Timer/Event Counter
Input/output Ports
SP
Reset configuration
Reset timing chart
Reset circuit
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
HT48CA3
July 16, 2003