HT48CA3 Holtek Semiconductor Inc, HT48CA3 Datasheet

Page 1

... ROM (8K 16 bits 3 banks) 224 8 data memory RAM General Description The HT48CA3 is an 8-bit high performance, RISC archi- tecture microcontroller device specifically designed for multiple I/O control product applications. The data ROM can be used to store remote control codes. This device is the mask version which is fully pin and functionally compatible with the OTP version HT48RA3 device ...

Page 2

... The pull-high resistor of this input/output line is also optional. PF0 is pin shared with the INT function pin. Positive power supply OSC1, OSC2 are connected network or Crystal (determined by hardware option) for the internal system clock. In the case of RC op- eration, OSC2 is the output terminal for 1/4 system clock. 2 HT48CA3 July 16, 2003 ...

Page 3

... Test Conditions Min. Typ. V Conditions DD 3V 400 3V 50% duty Without WDT prescaler 11.5 3V Without WDT prescaler 1024 1 Power-up, reset or 1024 wake-up from HALT HT48CA3 Ta=25 C Max. Unit ...

Page 4

... Program Counter S14~S0: Stack register bits @7~@0: PCL bits 4 HT48CA3 * July 16, 2003 ...

Page 5

... This feature prevents stack overflow al- lowing the programmer to use the structure more easily similar case, if the stack is full and a CALL is sub- Table Location * Table location @7~@0: Table pointer bits 5 HT48CA3 * July 16, 2003 ...

Page 6

... The data move- ment between two data memory locations must pass through the accumulator. Rev. 1.40 HT48CA3 RAM mapping Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: ...

Page 7

... When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further inter- rupts. Function Status register 7 HT48CA3 July 16, 2003 ...

Page 8

... OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscilla- tor, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a Function INTC register 8 HT48CA3 July 16, 2003 ...

Page 9

... HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others remain in their original status. The port A wake-up and interrupt methods can be con- sidered as a continuation of normal execution. Each bit Watchdog Timer 9 HT48CA3 CLR July 16, 2003 ...

Page 10

... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. Rev. 1.40 HT48CA3 The functional unit chip reset status are shown below. PC 000H Interrupt Disable ...

Page 11

... PFC ---- ---1 ---- ---1 TBHP xxxx xxxx uuuu uuuu Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.40 HT48CA3 RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...

Page 12

... In the case of counter overflows, the counter 0 is reloaded from the Timer/Event Counter 0 preload Rev. 1.40 HT48CA3 register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; ...

Page 13

... In the case of Timer/Event Counter 1 OFF condition, writing data to the Timer/Event Counter 1 preload regis- ter will also load the data to Timer/Event Counter 1. But if the Timer/Event Counter 1 is turned on, data written to the Timer/Event Counter 1 will only be kept in the Timer/Event Counter 0 Timer/Event Counter 1 13 HT48CA3 July 16, 2003 ...

Page 14

... If the con- trol register bit is 0, the contents of the latches will move to internal data bus ( mov and read-modify-write in- Rev. 1.40 HT48CA3 structions). The input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. For output function, CMOS is the only configuration ...

Page 15

... PA pull-high enable or disable: Byte option PF pull-high enable or disable PB pull-high (PB0~PB3, PB4~PB7) enable or disable: Nibble option PB0 or PFD CLR WDT instructions System oscillators crystal WDT enable or disable WDT clock source: WDTOSC or system clock/4 (T1D) Rev. 1.40 Input/output ports Function 15 HT48CA3 July 16, 2003 ...

Page 16

... Crystal & Resonator (2 pin) 1MHz Crystal 429kHz Resonator 455kHz Resonator 480kHz Resonator Rev. 1.40 Crystal or Ceramic Resonator for Multiple I/O Applications C* R* 0pF 10k 0pF 12k 10pF 12k 0pF 10k 25pF 10k 25pF 10k 35pF 27k 300pF 10k 300pF 10k 300pF 9.1k 16 HT48CA3 July 16, 2003 ...

Page 17

... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.40 Instruction Description 17 HT48CA3 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 ...

Page 18

... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged. Rev. 1.40 Instruction Description 18 HT48CA3 Flag Cycle Affected 2 None (2) 1 None (2) 1 None ...

Page 19

... The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 20

... TC2 TC1 CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 21

... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 22

... The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TC2 TC1 Rev. 1. (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C HT48CA3 July 16, 2003 ...

Page 23

... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 24

... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 25

... The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 26

... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 27

... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TC2 TC1 Rev HT48CA3 July 16, 2003 ...

Page 28

... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TC2 TC1 Rev. 1. ([m]+ ([m]+ HT48CA3 July 16, 2003 ...

Page 29

... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TC2 TC1 Rev. 1. [m].7~[m].4 [m].3~[m]. HT48CA3 July 16, 2003 ...

Page 30

... TBLH directly. Operation [m] ROM code (low byte) TBLH code (high byte) Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 31

... Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TC2 TC1 Rev. 1. HT48CA3 July 16, 2003 ...

Page 32

... Package Information 28-pin SKDIP (300mil) Outline Dimensions Symbol Min. A 1375 B 278 C 125 D 125 295 I 330 0 Rev. 1.40 HT48CA3 Dimensions in mil Nom. Max. 1395 298 135 145 20 70 100 315 375 15 32 July 16, 2003 ...

Page 33

... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 697 Rev. 1.40 HT48CA3 Dimensions in mil Nom. Max. 419 300 20 713 104 July 16, 2003 ...

Page 34

... Product Tape and Reel Specifications Reel Dimensions SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.40 HT48CA3 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 34 July 16, 2003 ...

Page 35

... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.40 HT48CA3 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 35 July 16, 2003 ...

Page 36

... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 HT48CA3 36 July 16, 2003 ...