HT46R52 Holtek Semiconductor, HT46R52 Datasheet - Page 7

• Manufacturer Part Number: HT46R52
• Description: (HT46R51 / HT46R52) A/D Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

Note:
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At the state of a subroutine call or an interrupt acknowl-
edgment, the contents of the program counter are
pushed onto the stack. At the end of the subroutine or an
interrupt routine, signaled by a return instruction (RET or
RETI), the program counter is restored to its previous
value from the stack. After a chip reset, the SP will point
to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt is
serviced. This feature prevents stack overflow, allowing
the programmer to use the structure more easily. If the
stack is full and a CALL is subsequently executed,
stack overflow occurs and the first entry will be lost (only
the most recent 6 return addresses are stored).
Data Memory - RAM
The data memory (RAM) is designed with 111 8 bits
and is divided into two functional groups, namely; spe-
cial function registers (23 8 bits) and general purpose
data memory (88 8bit) most of which are read-
able/writable, although some are read only. Of the two
types of functional groups, the special function registers
consist of an Indirect addressing register 0 (00H), a
Memory pointer register 0 (MP0;01H), an Indirect ad-
dressing register 1 (02H), a Memory pointer register 1
(MP1;03H), an Accumulator (ACC;05H), a Program
counter lower-order byte register (PCL;06H), a Table
pointer (TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Status register (STATUS;0AH), an Inter-
rupt control register (INTC;0BH), a Timer/Event Counter
(TMR:0DH), a Timer/Event Counter control register
(TMRC;0EH), PWM data register (PWM;1AH), the A/D
Rev. 1.40
TABRDC [m]
TABRDL [m]
Instruction
b10~b0: Table location bits
P10~P8: Current program counter bits
@7~@0: Table pointer bits
For the Ht46R51, since the program counter is 10 bits wide (b0~b9), the b10 column in the table are not appli-
cable
For the HT46R52, since the program counter is 11 bits wide (b0~b10)
P10
b10
1
P9
b9
1
b8
P8
1
@7
@7
b7
Table Location
@6
@6
b6
7
Table Location
@5
@5
b5
@4
@4
b4
RAM Mapping
@3
@3
b3
HT46R51/HT46R52
@2
@2
b2
@1
@1
b1
July 12, 2005
@0
@0
b0