HT46C47 Holtek Semiconductor, HT46C47 Datasheet - Page 17

• Manufacturer Part Number: HT46C47
• Description: (HT46C46 / HT46C47) Cost-Effective A/D Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H or
18H) instructions.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 4-bit of port B and 7 bits of port D
are not physically implemented; on reading them a 0 is
returned whereas writing then results in a no-operation.
See Application note.
Each I/O line has a pull-high option. Once the pull-high
option is selected, the I/O line has a pull-high resistor,
otherwise, there s none. Take note that a non-pull-high
I/O line operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode always remain-
ing its original functions. Once the PFD option is se-
lected, the PFD output signal is controlled by PA3 data
register only. Writing 1 to PA3 data register will enable
the PFD output function and writing 0 will force the
PA3 to remain at 0 . The I/O functions of PA3 are
shown below.
Note:
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0. If the PWM function is en-
abled, the PWM signal will appear on PD0 (if PD0 is op-
erating in output mode). Writing 1 to PD0 data register
Rev. 1.00
Mode
PA3
I/O
The PFD frequency is the timer/event counter
overflowfrequency divided by 2.
(Normal)
Logical
Input
I/P
(Normal)
Logical
Output
O/P
Logical
(PFD)
Input
I/P
(Timer on)
(PFD)
PFD
O/P
HT46R46/HT46C46/HT46R47/HT46C47
17
will enable the PWM output function and writing 0 will
force the PD0 to remain at 0 . The I/O functions of PD0
are as shown.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
PWM
The microcontroller provides 1 channel (6+2) bits PWM
output shared with PD0. The PWM channel has its data
register denoted as PWM (1AH). The frequency source
of the PWM counter comes from f
is an eight bits register. The waveforms of PWM output
are as shown. Once the PD0 is selected as the PWM
output and the output function of PD0 is enabled
(PDC.0= 0 ), writing 1 to PD0 data register will enable
the PWM output function and writing 0 will force the
PD0 to stay at 0 .
A PWM cycle is divided into four modulation cycles
(modulation cycle 0~modulation cycle 3). Each modula-
tion cycle has 64 PWM input clock period. In a (6+2) bit
PWM function, the contents of the PWM register is di-
vided into two groups. Group 1 of the PWM register is
denoted by DC which is the value of PWM.7~PWM.2.
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a PWM cycle, the duty cycle of each modulation cycle
is shown in the table.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
Modulation cycle i
Mode
PD0
Modulation
I/O
Frequency
Parameter
f
SYS
(i=0~3)
PWM
/64
(Normal)
Logical
Input
I/P
PWM Cycle
Frequency
(Normal)
Logical
Output
f
SYS
AC (0~3)
O/P
i<AC
i AC
/256
SYS
(PWM)
Logical
December 28, 2004
Input
. The PWM register
I/P
PWM Cycle
[PWM]/256
Duty Cycle
DC+1
Duty
DC
64
64
(PWM)
PWM
O/P