HT46C47 Holtek Semiconductor, HT46C47 Datasheet - Page 11

• Manufacturer Part Number: HT46C47
• Description: (HT46C46 / HT46C47) Cost-Effective A/D Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), A/D converter request
flag (ADF), enable timer/event counter bit (ETI), enable
external interrupt bit (EEI), enable A/D converter inter-
rupt bit (EADI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC) which is
located at 0BH in the data memory. EMI, EEI, ETI, EADI
are used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF, EIF, ADF)
are set, they will remain in the INTC register until the in-
terrupts are serviced or cleared by a software instruc-
tion.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se-
lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30k
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
Rev. 1.00
External Interrupt
Timer/Event Counter Overflow
A/D Converter Interrupt
Interrupt Source
System Oscillator
to 750k . The system clock, divided
Priority
1
2
3
Vector
0CH
04H
08H
HT46R46/HT46C46/HT46R47/HT46C47
11
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating fre-
quency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65 s@5V. The WDT oscillator
can be disabled by options to conserve power.
Watchdog Timer - WDT
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by an op-
tion. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
Once the internal oscillator (RC oscillator with a period
of 65 s@5V normally) is selected, it is divided by
32768~65536 to get the time-out period of approxi-
mately 2.1s~4.3s. This time-out period may vary with
temperatures, VDD and process variations. If the WDT
oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the HALT state the WDT may stop count-
ing and lose its protecting purpose. In this situation the
logic can only be restarted by external logic.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
mode, the overflow will initialize a warm reset , and
only the program counter and SP are reset to zero. To
clear the contents of WDT, three methods are adopted;
external reset (a low level to RES), software instruction
and a HALT instruction. The software instruction include
WDT2 . Of these two types of instruction, only one can
be active depending on the options
selection option . If the CLR WDT is selected (i.e. CLR
WDT times equal one), any execution of the CLR
WDT instruction will clear the WDT. In the case that
WDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may re-
set the chip as a result of time-out.
chip reset and set the status bit TO . But in the HALT
CLR WDT and the other set
CLR WDT1 and CLR WDT2 are chosen (i.e. CLR
CLR WDT1 and CLR
December 28, 2004
CLR WDT times