HT46C47 Holtek Semiconductor, HT46C47 Datasheet
HT46C47
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HT46C47 Summary of contents
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... rchi tectur e microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46C46, HT46C47 are fully pin and functionally com- patible with the OTP version HT46R46, HT46R47 de- vice. Rev. 1.00 ...
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... Block Diagram Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 2 December 28, 2004 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Description +6.0V Storage Temperature ............................ 125 ...
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... LVR I I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH V A/D Input Voltage AD E A/D Conversion Error AD Additional Power Consumption I ADC if A/D Converter is Used Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Test Conditions Min. Typ. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V 0.6 No load, f =4MHz SYS ADC disable ...
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... AD1 for HT46R46/HT46C46 A/D Clock Period t AD2 for HT46R47/HT46C47 A/D Conversion Time t ADC1 for HT46R46/HT46C46 A/D Conversion Time t ADC2 for HT46R47/HT46C47 A/D Sampling Time t ADCS1 for HT46R46/HT46C46 A/D Sampling Time t ADCS2 for HT46R47/HT46C47 Note: *t =1/f SYS SYS Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Test Conditions Min. Typ. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. ...
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... Return from Subroutine S10 Note: *10~*0: Program counter bits #10~#0: Instruction code bits For the HT46R47/HT46C47, the Program Counter is 11 bits wide, i.e. from *10~*0. For the HT46R46/HT46C46, the Program Counter is 10 bits wide, the *10 the column in the table is not applicable. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 incremented by one. The program counter then points to the memory word containing the next instruction code ...
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... Note: *10~*0: Table location bits @7~@0: Table pointer bits For the HT46R47/HT46C47, the Table address location is 11 bits, i.e. from *10~*0. For the HT46R46/HT46C46, the Table address location is 10 bits, i.e. from *9~*0. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 If the main routine and the ISR (Interrupt Service Rou- tine) both employ the table read instruction, the con- tents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR ...
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... This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 4 levels for the HT46R46/ HT46C46 or 6 levels for the HT46R47/HT46C47 and are neither part of the data nor part of the program space, and is neither readable nor writeable. The acti- vated level is indexed by the stack pointer (SP) and is neither readable nor writeable ...
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... RAM Mapping for the HT46R47/HT46C47 Bit No. Label C is set if an operation results in a carry during an addition operation borrow does not take 0 C place during a subtraction operation, otherwise C is cleared also affected by a rotate through carry instruction set if an operation results in a carry out of the low nibbles in addition or no borrow from the ...
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... A/D converter request flag (1=active; 0=inactive) 7 Unused bit, read as 0 Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance ...
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... VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accu- rate oscillator frequency is desired. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 If the Crystal oscillator is used, a crystal across OSC1 Vector and OSC2 is needed to provide the feedback and phase 04H ...
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... If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Watchdog Timer Once a wake-up event occurs, it takes 1024 t tem clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up ...
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... WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode SP Points to the top of the stack Reset Timing Chart Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Configuration 13 ...
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... ADCR 0100 0000 0100 0000 ACSR 1--- --00 1--- --00 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 RES Reset RES Reset WDT Times-out (Normal Operation) (HALT) -uuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu 000H 000H ...
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... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once over- flow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt re- quest flag (TF ...
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... There are 13 bidirectional input/output lines in the microcontroller, labeled as PA, PB and PD, which are mapped to the data memory of [12H], [14H] and [18H] Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Timer/Event Counter respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 18H) ...
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... PD0. If the PWM function is en- abled, the PWM signal will appear on PD0 (if PD0 is op- erating in output mode). Writing 1 to PD0 data register Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 will enable the PWM output function and writing 0 will force the PD0 to remain The I/O functions of PD0 are as shown. ...
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... A/D Converter The 4 channels and 8-bit resolution for the HT46R46/ HT46C46 or 9-bit resolution for the HT46R47/HT46C47 A/D converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter con- tains 3 special registers for the HT46R46/HT46C46 which are; ADR (21H), ADCR (22H) and ACSR (23H) or contains 4 special registers for the HT46R47/HT46C47 whice are ...
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... Select the A/D converter clock source SYS 0 ADCS0 SYS 1 ADCS1 /32 SYS 1, 1: Undefined, cannot be used. 2~6 Unused bit, read TEST For internal test only. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Function ADCR (22H) Register Function ACSR (23H) Register A/D Conversion Timing 19 December 28, 2004 ...
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... Polling_EOC: sz ADCR.6 ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADR ; read conversion result from the ADR (HT46R46/HT46C46 ADRH, ADRL (HT46R47/HT46C47) register mov adr_buffer,a ; save result to user defined register : : jmp start_conversion ; start next A/D conversion Example: using Interrupt method to detect end of conversion set INTC.0 ...
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... PWM enable or disable 7 PA0~PA7 wake-up: enable or disable 8 PFD enable or disable 9 Low voltage reset selection: enable or disable LVR function. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 The relationship between V and V DD Note the voltage range for proper chip OPR operation at 4MHz system clock. Low Voltage Reset ...
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... The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 C1 0pF 10k ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Instruction Description 23 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Instruction Description 24 Flag Cycle Affected 2 None (2) 1 ...
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... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 addr ...
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... PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Program Counter addr OV Z ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Program Counter+1 OV ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Stack Stack ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ([m]+1) ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 ...
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... Package Information 18-pin DIP (300mil) Outline Dimensions Symbol Min. A 895 B 240 C 125 D 125 295 I 335 0 Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Dimensions in mil Nom. Max. 915 260 135 145 100 315 375 15 38 December 28, 2004 20 70 ...
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... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 447 Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Dimensions in mil Nom. Max. 419 300 460 104 December 28, 2004 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 18W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 40 December 28, 2004 ...
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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 Dimensions in mm 24.0+0.3 0.1 16.0 0.1 1.75 0.1 11.5 0.1 1.5 0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 12.0 0.1 2.8 0.1 0.3 0.05 21.3 41 December 28, 2004 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT46R46/HT46C46/HT46R47/HT46C47 42 December 28, 2004 ...