74HCT40105D,112 NXP Semiconductors, 74HCT40105D,112 Datasheet - Page 13

• Manufacturer Part Number: 74HCT40105D,112
• Description: IC 4X16 FIFO REGISTER 16-SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT40105D,112

• Package / Case: 16-SOIC (3.9mm Width)
• Function: Asynchronous
• Memory Size: 64 (4 x 16)
• Data Rate: 25MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: HCT
• Number Of Circuits: 1
• Maximum Clock Frequency: 36 MHz
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 4.5 V
• Logic Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2839-5; 933715220112

Philips Semiconductors
With FIFO empty; SO is held HIGH in anticipation
agewidth
Shift-in operation; high-speed burst mode
1998 Jan 23
4-bit x 16-word FIFO register
(1) HC : V
Fig.10 Waveforms showing ripple through delay SI input to DOR output
(1) HC : V
Fig.11 Waveforms showing SI minimum pulse width and SI maximum
HCT : V
HCT : V
SO INPUT
DOR OUTPUT
Q OUTPUT
SI INPUT
n
and propagation delay from the DOR pulse to the Q
pulse frequency, in high-speed shift-in burst mode.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
1
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
V M
(1)
2
CC
CC
V M
.
.
(1)
ripple through
t PLH
delay
4
3
V M
(1)
t PHL / t PLH
5
13
t PHL
6
n
MBA337
output.
Notes to Fig.10
1. FIFO is initially empty, SO is held
2. SI pulse; loads data into FIFO
3. DOR flag signals the arrival of
4. Output transition; data arrives at
5. SO set LOW; necessary to
6. DOR goes LOW; FIFO is empty
Note to Fig.11
In the high-speed mode, the burst-in
rate is determined by the minimum
shift-in HIGH and shift-in LOW
specifications. The DIR status flag is
a don’t care condition, and a shift-in
pulse can be applied regardless of the
flag. A SI pulse which would overflow
the storage capacity of the FIFO is
ignored.
HIGH.
and initiates ripple through
process.
valid data at the output stage.
output stage after the specified
propagation delay between the
rising edge of the DOR pulse to
the Q
complete shift-out process. DOR
remains LOW, because FIFO is
empty.
again.
74HC/HCT40105
n
output.
Product specification