74HCT40105D,112 NXP Semiconductors, 74HCT40105D,112 Datasheet - Page 11

• Manufacturer Part Number: 74HCT40105D,112
• Description: IC 4X16 FIFO REGISTER 16-SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT40105D,112

• Package / Case: 16-SOIC (3.9mm Width)
• Function: Asynchronous
• Memory Size: 64 (4 x 16)
• Data Rate: 25MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: HCT
• Number Of Circuits: 1
• Maximum Clock Frequency: 36 MHz
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 4.5 V
• Logic Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2839-5; 933715220112

Philips Semiconductors
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
With FIFO full; SI held HIGH in anticipation of empty location
1998 Jan 23
4-bit x 16-word FIFO register
(1) HC : V
Fig.6
(1) HC : V
Fig.7
HCT : V
HCT : V
Waveforms showing the SI input to DIR output propagation
delay. The SI pulse width and SI maximum pulse frequency.
Waveforms showing bubble-up delay, SO input to DIR output
and DIR output pulse width.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
11
Notes to Fig.6
1. DIR initially HIGH; FIFO is
2. SI set HIGH; data loaded into
3. DIR drops LOW, input stage
4. DIR goes HIGH, status flag
5. SI set LOW; necessary to
6. Repeat process to load 2nd word
7. DIR remains LOW: with attempt
Notes to Fig.7
1. FIFO is initially, shift-in is held
2. SO pulse; data in the output
3. DIR HIGH; when empty location
4. DIR returns to LOW; FIFO is full
5. SI brought LOW; necessary to
prepared for valid data.
input stage.
“busy”.
indicates FIFO prepared for
additional data; data from first
location “ripple through”.
complete shift-in process.
through to 16th word into FIFO.
to shift into full FIFO, no data
transfer occurs.
HIGH.
stage is unloaded, “bubble-up
process of empty locations
begins”.
reached input stage, flag
indicates FIFO is prepared for
data input.
again.
complete whidt-in process, DIR
remains LOW, because FIFO is
full.
74HC/HCT40105
Product specification