TDA19989 NXP Semiconductors, TDA19989 Datasheet - Page 29

• Manufacturer Part Number: TDA19989
• Description: 150 MHz pixel rate HDMI 1.3 transmitter
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
8. I
TDA19989_1
Preliminary data sheet
2
C-bus interface and register definitions
8.1 I
8.2 Memory page management
The I
(400 kHz) and Standard mode (100 kHz) are supported.
The registers of TDA19989 can be accessed via the I
for those which are confidential.
HDMI and CEC cores I
Table 21.
Table 22.
For read access, the master writes the address of TDA19989 HDMI or CEC core, and the
subaddress to access the specific register and then the data.
The I
between pages is made with common register CURPAGE_ADR. It is only necessary to
write in this register once to change the current page. So multiple read or write operations
in the same page need a write register CURPAGE_ADR once at the beginning.
The following memory pages are available for TDA19989:
HDMI core address
A6
1
CEC core address
A6
0
2
Fig 17. I
•
•
•
•
•
•
•
C-bus protocol
Page 00h: general control
Page 02h: PLL settings
Page 09h: EDID control page
Page 10h: information frames and packets
Page 11h: audio settings and content info packets
Page 12h: HDCP and OTP'
Page 13h: gamut-related metadata packets
2
2
C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast mode
C-bus memory is split into several pages for HDMI core only, and the selection
2
HDMI core I
CEC core I
C-bus access
A5
1
A5
1
CSDA
CSCL
2
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Rev. 01 — 15 February 2010
SLAVE ADDRESS
C-bus address
2
A4
1
A4
1
2
C-bus address
C-bus addresses are given in
A3
0
A3
0
HDMI 1.3 transmitter with HDCP and CEC support
SUBADDRESS
A2
0
A2
1
2
C-bus. All registers are R/W except
Table 21
A1
0
A1
0
DATA
and
TDA19989
A0
0
A0
0
Table
001aal419
© NXP B.V. 2010. All rights reserved.
STOP
22.
R/W
0/1
R/W
0/1
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