IDT82V3280 Integrated Device Technology, IDT82V3280 Datasheet - Page 7

• Manufacturer Part Number: IDT82V3280
• Description: Wan Pll
• Manufacturer: Integrated Device Technology

IDT82V3280
WAN PLL
Table 49: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 153
Table 50: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 153
Table 51: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 153
Table 52: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 155
Table 53: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 156
Table 54: Output Clock Jitter Generation .................................................................................................................................................................. 157
Table 55: Output Clock Phase Noise ......................................................................................................................................................................... 158
Table 56: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 158
Table 57: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 158
Table 58: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 158
Table 59: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 158
Table 60: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 159
Table 61: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 159
Table 62: Input/Output Clock Timing 3 ...................................................................................................................................................................... 161
Table 63: Output Clock Timing .................................................................................................................................................................................. 162
List of Tables
7
June 19, 2006