IDT82V3280 Integrated Device Technology, IDT82V3280 Datasheet - Page 58

• Manufacturer Part Number: IDT82V3280
• Description: Wan Pll
• Manufacturer: Integrated Device Technology

6
dard except the following:
Table 41: JTAG Timing Characteristics
JTAG
IDT82V3280
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
The JTAG interface timing diagram is shown in
• The output boundary scan cells do not capture data from the
• The TRST pin is set low by default and JTAG is disabled in order
Symbol
core and the device does not support EXTEST instruction;
to be consistent with other manufacturers.
t
TCK
t
t
t
S
H
D
TCK
TMS
TDI
JTAG
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
TCK period
Parameter
TDO
t
S
Figure 26. JTAG Interface Timing Diagram
Figure
26.
t
H
58
t
TCK
Min
100
25
25
t
D
Typ
Max
50
June 19, 2006
Unit
ns
ns
ns
ns
WAN PLL