IDT71P72804 Integrated Device Technology, IDT71P72804 Datasheet - Page 3

• Manufacturer Part Number: IDT71P72804
• Description: 1.8v 1m X 18 Qdr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

Pin Definitions
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
BW
BW
Symbol
CQ, CQ
Q[X:0]
D[X:0]
2
K
0
SA
ZQ
W
R
C
, BW
, BW
C
K
3
1
Pin Function
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output Clock
Input Clock
Input Clock
Input Clock
Input Clock
Output
Input
Input
Input
Input
Input
Input
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
1M x 18 -- D[17:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K
clocks during write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data.
Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW
addresses are sampled on the rising edge of K clock during active write operations. These address inputs are
multiplexed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising
edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the
Read port is deselected, Q[X:0] are automatically three-stated.
operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause
D[X:0] to be ignored.
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read
operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is
allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock.
Each read access consists of a burst of two sequential transfer.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be
used together to deskew the flight times of various devices on the board back to the controller. See application example
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can
be used together to deskew the flight times of various devices on the board back to the controller. See application
example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out
data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs
and can be used as a data valid indication. These signals are free running and do not stop when the output data is tri-
stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance.
Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this
pin can be connected directly to V
directly to GND or left unconnected.
512K x 36 -- D[35:0]
512K x 36 -- BW
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write
the appropriate port is deselected.
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write
for further details.
through Q[X:0] when in single clock mode.
0
controls D[8:0] and BW
0
controls D[8:0], BW
DDQ
1
, which enables the minimum impedance mode. This pin cannot be connected
1
controls D[17:9], BW
controls D[17:9]
6.42
3
Description
2
controls D[26:18] and BW
Commercial and IndustrialTemperature Range
3
controls D[35:27]
6109 tbl 02a