IDT71P72804 Integrated Device Technology, IDT71P72804 Datasheet - Page 2

• Manufacturer Part Number: IDT71P72804
• Description: 1.8v 1m X 18 Qdr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

is precisely timed to the data output, and tuned with matching impedance
and signal quality. The user can use the echo clock for downstream
clocking of the data. Echo clocks eliminate the need for the user to
produce alternate clocks with precise timing, positioning, and signal quali-
ties to guarantee data capture. Since the echo clocks are generated by
the same source that drives the data output, the relationship to the data is
not significantly affected by voltage, temperature and process, as would
be the case if the clock were generated by an outside source.
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V V
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
and output ports simultaneously. All data is in two word bursts, with
addressing capability to the burst level.
Clocking
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
is, used to clock in the control signals (R, W and BWx), the read ad-
dress, and the first word of the data burst during a write operation. The
K clock is used to clock in the control signals (BWx), write address and
the second word of the data burst during a write operation. The K and
K clocks are also used internally by the SRAM. In the event that the user
disables the C and C clocks, the K and K clocks will also be used to clock
the data out of the output register and generate the echo clock. The C
and C clocks may be used to clock the data out of the output register
during read operations and to generate the echo clocks. C and C must
be presented to the SRAM within the timing tolerances. The output data
from the QDRII will be closely aligned to the C and C input, through the
use of an internal DLL. When C is presented to the QDRII SRAM, the
DLL will have already internally clocked the first data word to arrive at
the device output simultaneously with the arrival of the C clock.
The C clock and second data word of the burst will also correspond.
Single Clock Mode
C may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and K clocks.
DLL Operation
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
The QDRII has echo clocks, which provide the user with a clock that
All interfaces of the QDRII SRAM are HSTL, allowing speeds be-
The device is capable of sustaining full bandwidth on both the input
The QDRII SRAM has two sets of input clocks, namely the K, K
The K and K clocks are the primary device input clocks. The K clock
The QDRII SRAM may be operated with a single clock pair. C and
The DLL in the output structure of the QDRII SRAM can be used to
DD
DDQ
.
The output impedance
and a separate Vref,
6.42
2
Echo Clock
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte and nibble write signals can be used to prevent writing any indi-
vidual bytes, or combined to prevent writing one word of the burst.
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
with the C and C clocks.
and designating with the Byte Write inputs (BWx) which bytes are to be
written. The first word of the data must also be present on the data input
bus D[X:0]. Upon the rising edge of K the first word of the burst will be
latched into the input register. After K has risen, and the designated hold
times observed, the second half of the clock cycle is initiated by present-
ing the write address to the address bus SA[X:0], the BWx inputs for the
second data word of the burst, and the second data item of the burst to the
data bus D[X:0]. Upon the rising edge of K, the second word of the burst
will be latched, along with the designated address. Both the first and
second words of the burst will then be written into memory as designated
by the address and byte write enables.
Output Enables
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
state.
Programmable Impedance
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with V
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to V
The echo clocks, CQ and CQ, are generated by the C and C clocks
The echo clock is very closely aligned with the data, guaranteeing
QDRII devices internally store the two words of the burst as a single,
Read operations are initiated by holding the read port select (R) low,
The QDRII SRAM automatically enables and disables the Q[X:0]
An external resistor, RQ, must be connected between the ZQ pin on
Write operations are initiated by holding the write port select (W) low
Commercial and IndustrialTemperature Range
DDQ
= 1.5V. The output impedance is adjusted
DDQ
.