IDT71P72804 Integrated Device Technology, IDT71P72804 Datasheet - Page 12

• Manufacturer Part Number: IDT71P72804
• Description: 1.8v 1m X 18 Qdr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

AC Electrical Characteristics
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges)
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
10. The 250MHz speed grade is not available in the 512K x 36-bit option.
11. Industrial temperature range is not available for the 250MHz speed grade.
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
Clock Parameters
Output Parameters
Set-Up Times
Hold Times
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KHKH
KC var
KHKL
KLKH
KHKH
KHKH
KHCH
KC lock
KC reset
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
AVKH
IVKH
DVKH
KHAX
KHIX
KHDX
Symbol
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
Clock Cycle Time (K,K,C,C)
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K K,C C)
Clock to data clock (K C,K C)
DLL lock time (K, C)
K static to DLL reset
C,C HIGH to output valid
C,C HIGH to output hold
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
Data-in and BWx valid to K, K rising edge
K,K rising edge to address hold
K,K rising edge to R, W inputs hold
K, K rising edge to data-in and BWx hold
Clock to clock (K K,C C)
C HIGH to output High-Z
C HIGH to output Low-Z
Address valid to K,K rising edge
R, W inputs valid to K,K rising edge
Parameter
6.42
12
1024
-0.45
-0.45
-0.30
-0.45
Min.
4.00
0.00
0.35
0.35
0.35
0.35
0.35
0.35
1.60
1.60
1.80
1.80
30
250MHz
-
-
-
-
-
(10,11)
6.30
0.20
0.45
0.45
0.30
0.45
Max
1.80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Commercial and IndustrialTemperature Range
1024
-0.45
-0.45
-0.35
-0.45
Min.
5.00
2.00
2.00
2.20
2.20
0.00
0.40
0.40
0.40
0.40
0.40
0.40
30
-
-
-
-
-
200MHz
Max
7.88
0.20
2.30
0.45
0.45
0.35
0.45
(3,7)
(3,7)
(3,7)
(3,7)
(3,7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-0.50
-0.50
-0.40
-0.50
Min.
1024
6.00
2.40
2.40
2.70
2.70
0.00
0.50
0.50
0.50
0.50
0.50
0.50
30
-
-
-
-
-
167MHz
Max
8.40
0.20
2.80
0.50
0.50
0.40
0.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
6109 tbl 11
3,4,5
3,4,5
1,5
8
8
9
9
2
3
3
3
3
6
6