STD0550 ST Microelectronics, Inc., STD0550 Datasheet
STD0550
Related parts for STD0550
STD0550 Summary of contents
Page 1
... Embedded Emulation Resources with In-Situ Flash Programming Capabilities Professional Toolset Support Visual Debugger ANSI C Compiler and Libraries 1.8V and 3.3V Power supplies Eco Standby and Low Power modes 27-MHz Crystal Oscillator and VCXO for MPEG decoder Typical Power Consumption: 2.9 Watts 35x35, 532+36 balls PBGA Package STD0550 PRELIMINARY SPECIFICATION 1/32 ...
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... Kbytes SRAM 4 Kbytes I-cache 4 Kbytes D-cache Diagnostic Controller Interrupt Controller EMI1 Digital Video Output Gamma Correction Perfect Color Engine Line Format Converter and Output Scaler Data Selection and Output Interface STD0550 HOUT VOUT Output Clock 4 to 10-bit RGB Digital Video Outputs ...
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... STD0550 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Introduction .......................................................................................................................... 4 1.2 MPEG Video/Audio Decoder System ................................................................................... 5 1.2.1 MPEG Video Decoder ..........................................................................................................................................6 1.2.2 Digital Audio Decoder ...........................................................................................................................................6 1.2.3 Modem analog front-end interface ........................................................................................................................7 1.2.4 Slave CPU Memory subsystem ............................................................................................................................7 1.2.5 Serial communication ...........................................................................................................................................7 1.2.6 Hardware transport stream demultiplexer interface ..............................................................................................8 1.2.7 On-chip PLL ..........................................................................................................................................................8 1.2.8 Diagnostic controller (DCU) ..................................................................................................................................8 1.2.9 Interrupt subsystem, Slave CPU ...........................................................................................................................8 1.2.10 PAL/NTSC/SECAM encoder .................................................................................................................................9 1 ...
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... General Description 1.1 Introduction The STD0550 is dedicated to iDTV, LCD and Matrix Display. Combined with an external audio processor STV82x7, it provides cost effective high performance solution for LCD-iDTV applications with resolution from VGA (640 x 480 WXGA (1366 x 768). It includes an MPEG decoder system, with its slave controller. The Transport stream is demultiplexed and demodulated ...
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... DMAs Communications arbiter ST20 arbiter and memory controller SDRAM I/F CD FIFOs 2D block move SDRAM arbiter (LMC) OSD, SP Video Video decoder filtering decoder and mixing STD0550 Hard Reset RID reset TAP Test Diagnostic controller JTAG debugging Cache subsystem interface Icache Refill SRAM control ...
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... STD0550 1.2.1 MPEG Video Decoder This is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video rates up to 720 x 480 and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and horizontal filters. The MPEG video decoder includes a display unit with five display planes as shown in the figure below ...
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... The caches support burst accesses to the external memories for refill and write-back. Off-chip There are two off-chip memory interfaces: MPEG memory interface controls the movement of data between the STD0550 and 16, 32 128 Mbits of SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and the slave CPU working data. ...
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... One SSC supports full-duplex synchronous communication. 1.2.6 Hardware transport stream demultiplexer interface The STD0550 can be connected to a front-end through the following interfaces: transport stream serial interface, transport stream parallel interface. The PIO pins can be tri-stated under software control to support low cost DVB-CI implementations and similar module interfaces ...
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... UART (ASC), a dedicated programmable clock generator, and eight bits of parallel IO port. 1.3 PAL/SECAM/NTSC Analog Video Decoder The STD0550 includes a high-quality video front-end for processing all analog standards into a digitalized 4:2:2 YCrCb video format. It processes NTSC/PAL/SECAM CVBS signals, as well as conventional analog RGB or YCrCb signals. ...
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... General Description The STD0550 includes a 32-bit ST20 CPU core with all peripherals required for controlling the TV chassis. Teletext data is extracted from the incoming stream and decoded by the CPU. An embedded On-Screen Display (OSD) generator delivers the text and graphics. The Video Display Pipeline performs feature box image processing such as picture improvement, horizontal and vertical rescaling and Temporal Noise Reduction ...
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... Field merging for film sources 11/32 Figure 5: Architectural Block Diagram Video Picture Pipeline Compositor YSI CTI Comp. Cursor OSD Pipeline BG Plane ST20 Core Block Move TV Peripherals TV Chassis Control I/Os STD0550 bits R Digital bits Video G Output bits Communiction B CSA Perfect H/V Color DE Engine DLCK SDRAM EMI4 ...
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... STD0550 The following table shows typical de-interlacing modes, according to the input format: Panels & Output interlaced interlaced modes Video A+A*B*+B Or A+Med (A,B) VGA Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) XGA 720>1024 576>768 Note: 720 pixels/line refers to ITU-R BT 601/656 video input standard resolution. ...
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... TV set. The set of Service components included in the demonstration application are very useful for developing applications. 13/32 Figure 6: Global Software Architecture Application Level Chassis Control Services Graphics, Remote Control, Zapper Drivers I²C, OSD, SDIN, Audio, Video STD0550 STD0550 Decoders ...
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... STD0550 Application Layer which contains the software that defines the “Look & Feel” of the TV set. This layer, for instance, contains the components that are responsible for the following features: interpretation of user inputs, display and navigation functions and Teletext applications. STV API ...
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... PIO0[7] SC0_DETECT PIO1[0] SSC0_DATA (MTSROUT/MRSTIN) PIO1[1] SSC0_CLOCK PIO1[2] SC external clock PARA_DVALID PIO1[3] PIO1[4] UART2_RXD PIO1[5] PARA_SYNC Trigger in for DCU Trigger out for DCU PIO2[0] UART3_DATA (SC1_DATA) STD0550 Alternate Function Type Input Output EXT_AUD_CLK O EXT_AUD_DATA O I/O O I/O EXT_AUD_WCLK O O PWR PWR I PWR PWR ...
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... STD0550 Ball Ball Name W1 PIO2[1] H4 PIO2[2] H2 PIO2[3] H1 PIO2[4] F4 PIO2[5] F2 PIO2[6] L25 PIO2[7] K4 PIO3[0] K2 PIO3[1] K1 PIO3[2] L3 PIO3[3] L4 PIO3[4] L2 PIO3[5] L1 PIO3[6] M3 PIO3[7] E25, F23, F24, H23, H24, H25, K23, K25 PIO4[0:7] V1 PIO5[0] V2 PIO5[1] J3 PIO5[2] M25 1 PIO5[3] M26 PIO5[4] N26 PIO5[5] Auxiliary Clock (Digital Decoder) ...
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... IRQ[2] (MD_IRQ) Pulse width modula 0 HSYNC Pulse width modula 1 BOOTFROMRO M² Pulse width modula 2 VSYNC/ODDEVEN Test clock Test data in Test data out Test mode select Test reset I²S data FEC_DATA STD0550 Alternate Function Type Input Output O O I/O I/O NOT_SDRAM_CS I/O 1/ CHIPSEL. BANK3 I NOT_SDRAM_WE ...
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... STD0550 Ball Ball Name M2 B_BCLK M1 B_FLAG N3 B_SYNC Video DAC (Digital Decoder) T26 R_OUT T25 G_OUT T23 B_OUT R25 Y_OUT R26 C_OUT P24 CV_OUT R23 I_REF_RGB R24 V_REF_RGB P25 I_REF_YCC P23 V_REF_YCC K22 VDD_RGB P26 VSS_RGB L22 VDD_YCC M13 VSS_YCC Shared Memory Interface (Digital Decoder) ...
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... Alternate Function: PIO[0] Bus extension Horizontal Synchronization Pulse Output Alternate Function: PIO[1] Bus extension Vertical Synchronization Pulse Output Alternate Function: PIO[2] Bus extension Field (Parity) Output Signal Alternate Function: PIO[3] Bus extension STD0550 Alternate Function Type Input Output REF REF REF O ...
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... STD0550 Ball Ball Name Clock Signal Pins (analog decoder) AA22 XTALOUT AA23 XTALIN_CLKXTP Y23 CLKXTM Configuration Pins (analog decoder) Y22 TST_MODE AB3 SDA AA3 SCL AB22 NRESET W22 I2CADD Y25 CLKSEL D1 Standard Definition Digital Video Input Stage N24 VSYNC L24 HSYNC ...
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... Digital Video Output 27 Digital Video Output 28 Digital Video Output 29 Digital CMOS Clock Digital CMOS Data Enable Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 STD0550 Alternate Function Type Input Output ...
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... STD0550 Ball Ball Name AB2 PORTC0 AB1 PORTC1 AA4 PORTC2 AA2 PORTC3 AE7 PORTC4 AC7 PORTC5 AD7 PORTC6 AF6 PORTC7 AF7 PORTD0 AD8 PORTD1 AC8 PORTD2 AE8 PORTD3 AC2 PORTD4 AF3 PORTD5 AF8 PORTD6 AD1 PORTD7 External Memory Interface, Master CPU ...
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... Flash Chip Select SDRAM Chip Select SDRAM Row Address Strobe SDRAM Column Address Strobe / Flash Output Enable* SDRAM Byte Enable 0 SDRAM Byte Enable 1 Clock Output for SDRAM SDRAM Clock Feedback 27 MHz Crystal Input STD0550 Alternate Function Type Input Output ...
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... STD0550 Ball Ball Name N2 XTALOUT Y24 CLKXTM AA24 CLKXTP N4 SHIELD_PLL AB23 TCK AB24 TDI AC26 TDO AB25 TMS AC24 TRST AC25 NRESET Power Supply (Digital Decoder) E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, F5, G5, H5, J5 VDD3_3 E15, E16, E17, E18, E20, E21, E22, G22, F22 ...
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... V Analog Voltage Supply for PLL 3 Analog Ground Supply for PLL 3 1.8 V Analog Voltage Supply for PLL 2 Analog Ground Supply for PLL 2 1.8 V Analog Voltage Supply for PLL Analog Ground Supply for PLL STD0550 Alternate Function Type Input Output PWR PWR PWR PWR ...
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... STD0550 Ball Ball Name Power Supply (Video Display TV System, Digital Power Supplies) Y6, AA6, AA7, AA8, AA9, AA10, AA11, T11, R11, P11, N11, T12, R12, P12, N12, T13, R13, P13 VDD33_IO R6, T6, U6, V6, W6 VDD18_CORE Power Supply Ground N1, AA1, AE1, P2, B3, Y3, D4, J4, N4, AD4, C6, F6, G6, H6, J6, F7, G7, H7, J7, K7, L7, M7, N7, P7, R7, T7, U7, V7, W7, Y7, D8, ...
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... ADD SDR SDR SDR FLAS FLAS ADD R_15 R_0 AM_ AM_ AM_ H_D1 H_D8 R_13 STD0550 SMI_ SMI_ SPDI A ADR ADR F_O SMI_ DAC DAC B ADR _IRC _PC 2 LK MCL K D_P D_P D_P ...
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... Enhacers and Bitmap On-Screen Display. STD0100, Revision 1.0, Dec. 2003: MPEG Audio and Video Decoder. 4 Product Order Codes STD0550Z: Standard product; Dolby Digital and Macrovision Encoding not active. STD0550ZD: Dolby Digital (AC3) active. STD0550ZM: Macrovision Encoding active. STD0550ZDM: Dolby Digital and Macrovision Encoding active. ...
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... General Package Information 5 General Package Information 5.1 Package Mechanical Data Figure 8: 532-Ball Plastic Ball Grid Array Package with 36 Center Ball Option 29/32 STD0550 ...
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... STD0550 DATABOOK (mm) Dim. Min 0.360 A2 b 0.600 D 34.800 D1 E 34.800 .ddd 1 .eee 2 .fff 1. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e ...
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... Summary Of Changes 6 Summary Of Changes Rev. 0.1 First Draft. 0.2 Changes to Figure 1: STD0550 Block Diagram on page 1.0 Added ball list and ball configuration. Added 31/32 Main Changes 4. Chapter 4: Product Order Codes on page STD0550 Date November 2003 February 2004 28. February 2004 ...
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... STD0550 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...