SC26C94C1N Philips Semiconductors, SC26C94C1N Datasheet - Page 17

• Manufacturer Part Number: SC26C94C1N
• Description: Quad universal asynchronous receiver/transmitter QUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
The selected set of rates is available for use by the receiver and
transmitter.
ACR[6:4] – Counter/Timer Mode and Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source (see Table 4).
The I/O pins available for counter/timer clock source is I/O1a and
I/O1c. The counter/timer clock selection is connected to the I/O1 pin
and will accept the signal on this pin regardless of how it is
programmed by the I/OPCR.
Table 7.
ACR[3:0] – I/O1b, I/O0b, I/O1a, I/O0a Change-of-State Interrupt
Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register, ISR[7], to
be set and thus allow the Change of State Detectors to enter the
bidding process. If a bit is in the ‘on’ state, the setting of the
corresponding bit in the IPCR will also result in the setting of ISR[7],
which may result in the generation of an interrupt output if IMR[7] =
1. If a bit is in the ‘off’ state, the setting of that bit in the IPCR has no
effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7:4] – I/O1b, I/O0b, I/O1a, I/O0a Change-of-State Detectors
These bits are set when a change of state, as defined in the Input
Port section of this data sheet, occurs at the respective pins. They
are cleared when the IPCR is read by the CPU. A read of the IPCR
also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR[3:0] – I/O1b, I/O0b, I/O1a, I/O0a State of I/O Pins
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins
during the time the IPCR is read. The IPR is an unlatched register.
Data can change during a read.
ISR – Interrupt Status Register
Important: The setting of these bits and those of the IMR are
essential to the interrupt bidding process.
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the interrupt mask
register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’, then the interrupt source represented by this bit
is allowed to enter the interrupt arbitration process. It will generate
an interrupt (the assertion of INTRN low) only if its bid exceeds the
1995 May 1
The timer mode generates a squarewave
Quad universal asynchronous receiver/transmitter (QUART)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
[6:4]
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
ACR[6:4] C/T Clock and Mode Select
Mode
I/O1 pin
I/O1 pin divided by 16
TxC1XA clock of the transmitter
TxC1XB clock of the transmitter
I/O1 pin
I/O1 pin divided by 16
Crystal or external clock (X1/CLK)
Crystal or external clock (X1/CLK) divided
by 16
Clock Source
17
interrupt threshold value. If the corresponding bit in the IMR is a
zero, the state of the bit in the ISR has no effect on the INTRN
output. Note that the IMR does not mask the reading of the ISR; the
complete status is provided regardless of the contents of the IMR.
ISR[7] – I/O Change-of-State
This bit is set when a change-of-state occurs at the I/O1b, I/O0b,
I/O1a, I/O0a input pins. It is reset when the CPU reads the IPCR.
ISR[6] – Channel b Change in Break
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command.
ISR[5] – Receiver Ready or FIFO Full Channel b
Normally the ISR[5] bit being set to one indicates the RxFIFO is
filled with one or more bytes and/or the receiver watch dog timer
(when enabled) has timed out.
The meaning of ISR[5] is controlled by the MR0[6] and MR1[6] bits
which are normally set to 00. The ISR[5] bit setting to one allows
the receiver to present its bid to the arbitration logic. This function is
explained in the “Interrupt Note On 26C94” and under the “Receiver
Interrupt Fill Level”.
ISR[5], if set, will reset when the RxFIFO is read. If the reading of
the FIFO does not reduce the fill level below that determined by the
MR bits, then ISR[5] sets again within two X1 clock times. Further, if
the MR fill level is set at 8 bytes AND there is a byte in the receiver
shift register waiting for an empty FIFO location, then a read of the
RxFIFO will cause ISR[5] to reset. It will immediately set again upon
the transfer of the character in the shift register to the FIFO.
NOTE: The setting of ISR[5] means that the receiver has entered
the bidding process. It is necessary for this bit to set for the receiver
to generate an interrupt. It does not mean it is generating an
interrupt.
ISR[4] – Transmitter Ready Channel b
The function of this bit is programmed by MR0[5:4] (normally set to
00). This bit is set when ever the number of empty TxFIFO
positions exceeds or equals the level programmed in the MR0
register. This condition will almost always exist when the transmitter
is first enabled. It will reset when the empty TxFIFO positions are
reduced to a level less than that programmed in MR0[5:4] or the
transmitter is disabled or reset.
The ISR[4] bit will reset with each write to the TxFIFO. If the write to
the FIFO does not bring the FIFO above the fill level determined by
the MR bits, the ISR[4] bit will set again within two X1 clock times.
NOTE: The setting of ISR[4] means that the transmitter has entered
the bidding process. It is necessary for this bit to set for the
transmitter to generate an interrupt. It does not mean it is
generating an interrupt.
ISR[3] – Counter Ready
In the counter mode of operation, this bit is set when the counter
reaches terminal count and is reset when the counter is stopped by
a stop counter command. It is initialized to ‘0’ when the chip is reset.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time the C/T reaches zero count). The bit
is reset by a stop counter command. The command, however, does
not stop the C/T.
ISR[2] – Channel a Change in Break
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command.
Product specification
SC26C94