SC26C94C1N Philips Semiconductors, SC26C94C1N Datasheet - Page 14

• Manufacturer Part Number: SC26C94C1N
• Description: Quad universal asynchronous receiver/transmitter QUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
In the “Block Error” mode the ORing of the error status bits and the
presentation of them to the status register takes place as the bytes
enter the RxFIFO. This allows an indication of problem data when
the error occurs after the leading bytes have been received. In the
character mode the error bits are presented to the status register
when the corresponding byte is at the top of the FIFO.
MR1[4:3] – Parity Mode Select
If “with parity” or “force parity” is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake-up mode (see ‘Wake-Up Mode’).
MR1[2] – Parity Type Select
This bit selects the parity type (odd or even) if the “with parity” mode
is programmed by MR1[4:3], and the polarity of the forced parity bit
if the “force parity” mode is programmed. It has no effect if the “no
parity” mode is programmed. In the special “wake-up” mode, it
selects the polarity of the transmitted A/D bit.
MR1[1:0] – Bits per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2 – Mode Register 2
MR2 is accessed when the channel MR pointer points to MR2,
which occurs after any access to MR1. Accesses to MR2 do not
change the pointer.
MR2[7:6] – Mode Select
The QUART can operate in one of four modes. MR2[7:6] = 00 is the
normal mode, with the transmitter and receiver operating
independently. MR2[7:6] = 01 places the channel in the automatic
echo mode, which automatically re-transmits the received data. The
following conditions are true while in automatic echo mode:
1. Received data is re-clocked and retransmitted on the TxD
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter need not be
4. The TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for
Two diagnostic modes can also be selected. MR2[7:6] = 10 selects
local loopback mode. In this mode:
1. The transmitter output is internally connected to the receiver
2. The transmit clock is used for the receiver.
3. The TxD output is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the receiver need not be
6. CPU to transmitter and receiver communications continue
The second diagnostic mode is the remote loopback mode, selected
by MR2[7:6] = 11. In this mode:
1995 May 1
1. Received data is re-clocked and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
4. The received parity is not checked and is not regenerated for trans-
5. The receiver must be enabled, but the transmitter need not be en-
Quad universal asynchronous receiver/transmitter (QUART)
output.
enabled.
transmission, i.e., transmitted parity bit is as received.
input.
enabled.
normally.
conditions are inactive.
mission, i.e., the transmitted parity bit is as received.
abled.
14
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected, the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes; if the
deselection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop bit has been retransmitted.
MR2[5] – Transmitter Request-to-Send Control
NOTE: When the transmitter controls the I/O2 pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather it signals that the transmitter has finished transmission.
(i.e., end of block).
This bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2[5] = 1
causes RTSN to be reset automatically one bit time after the
characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission as follows:
1. Program auto-reset mode: MR2[5] = 1.
2. Enable transmitter.
3. Assert RTSN via command.
4. Send message.
5. Disable the transmitter after the last byte of the message is
6. The last character will be transmitted and RTSN will be reset one
MR2[4] – Transmitter Clear-to-Send Flow Control
The sate of this bit determines if the CTSN input (I/O0) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the sate of CTSN
each time it is ready to send a character. If it is asserted (Low), the
character is transmitted. If it is negated (High), the TxD output
remains in the marking state and the transmission is delayed until
CTSN goes Low. Changes in CTSN, while a character is being
transmitted do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1–1/16 to
2 stop bits can be programmed in increments of 1/16 bit. If an
external 1X clock is used for the transmitter, MR2[3] = 0 selects one
stop bit and MR2[3] = 1 selects two stop bits to be transmitted.
RECEIVER NOTE: In all cases, the receiver only checks for a
“mark” condition at the center of the stop bit (1/2 to 9/16 bit
time into the stop bit position). At this time the receiver has
6. Character framing is not checked, and the stop bits are retrans-
7. A received break is echoed as received until the next valid start bit
mitted as received.
is detected.
loaded to the TxFIFO. At the time the disable command is
issued, be sure that the transmitter ready bit is on and the
transmitter empty bit is off. If the transmitter empty bit is on (the
indication of transmitter underrun) when the disable is issued,
the last byte(s) will not be sent.
bit time after the last stop bit.
Product specification
SC26C94