ISL8102 Intersil Corporation, ISL8102 Datasheet - Page 22

• Manufacturer Part Number: ISL8102
• Description: Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

The compensation network consists of the error amplifier
(internal to the ISL8102) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
phase margin (better than 45 degrees). Phase margin is the
difference between the closed loop phase at F
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
and C
locating the poles and zeros of the compensation network:
1. Select a value for R
FIGURE 22. VOLTAGE-MODE BUCK CONVERTER
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R
multiplied by a factor of (R
of the calculations remain unchanged, as long as the
compensated R
R
CIRCUIT
2
PWM
3
) in Figures 20 and 21. Use the following guidelines for
=
-------------------------------------------- -
d
V
COMP
MAX
OSC
0
; typically 0.1 to 0.3 of F
COMPENSATION DESIGN
2
HALF-BRIDGE
⋅
OSCILLATOR
V
for desired converter bandwidth (F
⋅
V
R
IN
OSC
E/A
DRIVE
1
2
⋅
⋅
R
F
value is used.
F
ISL8102
2
LC
0
1
C
+
-
(1kΩ to 5kΩ, typically). Calculate
VREF
+
2
-
C
22
1
P1
FB
UGATE
PHASE
LGATE
VSEN
VDIFF
RGND
+R
EXTERNAL CIRCUIT
2
S1
value needs be
SW
R
)/R
3
V
IN
) and adequate
R
P1
1
1
1
, R
-R
C
. The remainder
L
3
0dB
3
2
, C
, R
DCR
and 180°.
V
1
3
ESR
OUT
-C
0
, C
C
). If
3
1
, C
2
ISL8102
,
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 23 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
G
F
F
2. Calculate C
3. Calculate C
4. Calculate R
Z1
Z2
MOD
G
G
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
FB
CL
C
C
R
C
=
=
1
2
3
3
f ( )
f ( )
f ( )
------------------------------ -
2π R
-------------------------------------------------
2π
=
=
=
=
=
=
=
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
F
----------- - 1
------------------------------------------------ -
2π R
⋅
⋅
F
(
SW
SW
LC
------------------------------------------------------------------------------------------------------------------------ -
(
G
1
R
d
----------------------------- -
--------------------------------------------------- - ⋅
s f ( ) R
R
2
1
⋅
⋅
⋅
MAX
1
1
MOD
1
⋅
V
+
). F
–
+
P2
C
1
+
1
2
2
2
3
3
OSC
⋅
s f ( ) R
R
1
such that F
⋅
⋅
⋅
s f ( ) R
such that F
such that F
1
FB
1
0.5 F
C
SW
0.7 F
⋅
is placed below F
3
C
f ( ) G
1
V
) C
1
1
⋅
⋅
) and closed-loop response (G
IN
⋅
⋅
⋅
(
⋅
LC
⋅
⋅
represents the per-channel switching
C
F
1
3
⋅
P2
3
2
CE
1
FB
LC
SW
+
---------------------------------------------------------------------------------------------------------- -
1
⋅
(to adjust, change the 0.5 factor to
⋅
+
C
s f ( )
+
C
against the capabilities of the error
f ( )
–
C
3
s f ( )
1
Z1
)
P1
1
Z2
2
F
F
⋅
)
⋅
P1
P2



is placed at a fraction of the F
(
1
is placed at F
is placed at F
⋅
R
(
+
1
ESR
=
=
where s f ( )
+
s f ( ) R
1
SW
-------------------------------------------- -
2π R
------------------------------ -
2π R
CE
R
+
3
s f ( ) ESR C
+
⋅
⋅
⋅
/F
) C
(typically, 0.5 to 1.0
DCR
⋅
1
,
LC
P2
MOD
2
2
3
⋅
⋅
3
⋅
⋅
1
, the lower the F



lower in frequency
-------------------- -
C
C
C
LC
CE
LC
-------------------- -
C
C
) C
1
3
1
), feedback
=
⋅
1
1
).
+
. Calculate C
⋅
.
+
⋅
⋅
2π f j
C
C
C
+
C
October 19, 2005
2
2
2
s
2
⋅ ⋅
CL



2



f ( ) L C
):
FN9247.0
⋅
LC
⋅
Z1
3
,