ISL8102 Intersil Corporation, ISL8102 Datasheet - Page 17

• Manufacturer Part Number: ISL8102
• Description: Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

proportional to the output current, the overcurrent trip level,
I
as shown in Equation 13.
Once the output current exceeds the overcurrent trip level,
V
the converter to begin overcurrent protection procedures. At
the beginning of overcurrent shutdown, the controller turns
off both upper and lower MOSFETs. The system remains in
this state for a period of 4096 switching cycles. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start (as shown in Figure 14). If the fault
remains, the trip-retry cycles will continue indefinitely until
either the controller is disabled or the fault is cleared. Note
that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for many applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
R
MAX
DROOP
OCSET
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
0A
0V
, can be set by selecting the proper value for R
=
will exceed V
I
--------------------------------------------------------- -
MAX
OUTPUT VOLTAGE
OUTPUT CURRENT
100µA R
⋅
R
COMP
OCSET
⋅
S
⋅
DCR
17
, and a comparator will trigger
OCSET
(EQ. 13)
,
ISL8102
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25 and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
Lower MOSFET Power Calculation
The calculation for the approximate power loss in the lower
MOSFET can be simplified, since virtually all of the loss in
the lower MOSFET is due to current conducted through the
channel resistance (r
maximum continuous output current, I
inductor current (see Equation 1), and d is the duty cycle
(V
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, F
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
Upper MOSFET Power Calculation
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-
recovery charge, Q
conduction loss.
P
P
LOW 1
OUT
LOW 2
,
,
/V
IN
=
=
).
r
V
DS ON
SW
D ON
(
DS(ON)
(
·
, and the length of dead times, t
IN
) during switching. Since a substantially
)
)
⋅
⋅
rr
F
, and the upper MOSFET r
DS(ON)



SW
I
----- -
losses, a large portion of the upper-
N
M



⋅
2
M
⋅


, V
(
I
----- -
). In Equation 14, I
N
1 d
M
D(ON)
–
+
I
-------- -
)
PP
2
+
 t

I
------------------------------------ -
, the switching
L PP
⋅
,
PP
2
d1
LOW,1
is the peak-to-peak
12
+
⋅
(


1 d
I
----- -
N
M
–
and P
–
M
d1
DS(ON)
)
I
-------- -
October 19, 2005
PP
2
is the
and t
 t

LOW,2
⋅
(EQ. 15)
(EQ. 14)
FN9247.0
d2
d2
, at
.