ISL8102 Intersil Corporation, ISL8102 Datasheet - Page 18

• Manufacturer Part Number: ISL8102
• Description: Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET reverse-
recovery charge, Q
commutated to the upper MOSFET before the lower-
MOSFET body diode can recover all of Q
through the upper MOSFET across VIN. The power
dissipated as a result is P
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of two drivers
in the controller package, the total power dissipated by both
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 5x5 QFN package is approximately 4W at
room temperature. See Layout Considerations paragraph for
thermal transfer improvement suggestions.
P
P
P
P
UP 1 ,
UP 2 ,
UP 3 ,
UP 4 ,
≈
≈
≈
=
V
r
V
DS ON
V
IN
IN
IN
(
⋅
⋅




⋅
I
----- -
Q
N
I
----- -
N
M
M
)
rr
⋅
+
–
UP,4
⋅



I
-------- -
I
-------- -
F
PP
PP
I
----- -
2
2
rr
N
M
SW
. Since the inductor current has fully







.
2
⋅
⋅
⋅






d
t
----
t
----
2
2
2
1
UP,3
+






I
--------- -
⋅
UP,2
PP
12
⋅
18
F
F
2
.
2
SW
. In Equation 17, the
SW
.
UP,1
1
rr
, it is conducted
and the
.
(EQ. 16)
(EQ. 17)
(EQ. 18)
(EQ. 19)
ISL8102
When designing the ISL8102 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
In Equations 20 and 21, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
N
respectively; N
I
without capacitive load and is typically 75mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
P
the power will be dissipated by the external gate resistors
(R
R
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, P
estimated as:
P
I
P
Q*
DR
P
P
Qg_TOT
DR_LOW
Qg_TOT
Q2
GI2
P
DR_LOW
G1
Qg_Q1
Qg_Q2
P
VCC product is the quiescent power of the controller
DR_UP
R
BOOT
=
are the number of upper and lower MOSFETs per phase,
EXT1
) of the MOSFETs. Figures 15 and 16 show the typical
P
and R


DR
3
-- - Q
2
, due to the gate charge of MOSFETs and the
⋅
=
=
=
, and in the boot strap diode, P
=
=
=
=
=
3
-- - Q
2
Q
G2
P
G1



P
P
---------------------



R
Qg_Q1
G2
⋅
--------------------------------------
R
--------------------------------------
R
DR_UP
Qg_Q1
G1
PHASE
) and the internal gate resistors (R
⋅
HI1
HI2
N
3
G1
⋅
Qg_Q2
+
PVCC F
Q1
R
DR_UP
R
+
+
R
-------------
⋅
N
HI1
HI2
+
PVCC F
R
+
R
GI1
Q1
+
P
is the number of active phases. The
EXT1
Q
EXT2
P
Qg_Q2
G1
G2
⋅
is the total lower gate drive power
DR_LOW
, the lower drive path resistance,
Qg_Q1
SW
⋅
⋅
and Q
+
+
N
--------------------------------------- -
R
SW
--------------------------------------- -
R
+
Q2
⋅
LO1
LO2
N
I
Q
 N

R
Q2
⋅
is the total upper gate drive
G2
+
⋅
R
R
⋅
N
EXT2
VCC
P
+
LO1
+
LO2
Q1
⋅
) is defined at the
PHASE
BOOT
R
N
R
Q
PHASE
EXT1
EXT2
⋅
is the driver total
N
=
PHASE
BOOT
DR
R
+
 P


⋅
 P


G2
(
F
, can be roughly
⋅
I
⋅
Q
SW
---------------------
---------------------
+
. The rest of
Qg_Q1
Qg_Q2
•
R
-------------
VCC
3
N
2
October 19, 2005
+
GI1
GI2
Q2
I
Q
(EQ. 22)
(EQ. 20)
(EQ. 21)
and
Q1
)
FN9247.0
and