ISL6721 Intersil Corporation, ISL6721 Datasheet - Page 16

• Manufacturer Part Number: ISL6721
• Description: Flexible Single Ended Current Mode PWM Controller
• Manufacturer: Intersil Corporation

the remaining pole and zero for the compensator are located
at:
f
f
The ratio of R15 to the parallel combination of R17 and R18
determine the mid band gain of the error amplifier.
A
From (EQ. 27), it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum Vin, maximum load, maximum Cout, and minimum
ESR.
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the
bandwidth to about Fsw/4. For this example, the bandwidth
will be further limited due to the low GBWP of the LM431-
based Error Amplifier and the opto-coupler. A bandwidth of
approximately 5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C14 is an integrating capacitor). The first
zero is placed below the crossover frequency, f
around 1/3 f
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R17 = R18 = R15 = 1kΩ
R20 = open
C13 = 100nF
C14 = 100pF
pc
zc
midband
=
=
------------------------------------------------------------
2 π R
------------------------------------------- -
2 π R
•
•
=
•
•
C
co
R
----------------------------------------------- -
1
13
15
15
15
. The second pole is placed at the lower of the
+
•
R
•
•
C
C
C
17
(
R
14
13
14
•
17
•
R
+
C
18
R
13
18
≈
)
------------------------------------------- -
2 π R
16
•
•
1
15
•
C
14
co
, usually
(EQ. 28)
(EQ. 29)
(EQ. 30)
ISL6721
A Bode plot of the closed loop system at low line, max load
appears below.
100
200
150
100
-100
10
20
30
40
50
200
150
100
50
40
30
20
10
50
-50
50
-10
-20
-30
-40
-50
50
50
40
30
20
10
0
0
0
0
0.01
0.01
0.01
0.01
FIGURE 9B. PHASE MARGIN
FIGURE 9A. GAIN
0.1
0.1
Frequency (kHz)
0.1
0.1
Frequency (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
1
1
1
1
10
10
10
10
100
100
100
100