ISL6721 Intersil Corporation, ISL6721 Datasheet - Page 10

• Manufacturer Part Number: ISL6721
• Description: Flexible Single Ended Current Mode PWM Controller
• Manufacturer: Intersil Corporation

results in a control loop that behaves more as a voltage
mode controller than as current mode controller.
The minimum amount of capacitance to place at the SLOPE
pin is:
where ton is the On time and Vslope is the amount of voltage
to be added as slope compensation to the current feedback
signal. In general, the amount of slope compensation added
is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
Switching Frequency, Fsw = 250kHz
Duty Cycle, D = 60%
ton = D/Fsw = 0.6/250E3 = 2.4µS
toff = (1 - D)/Fsw = 1.6µS
Determine the downslope:
Downslope = 0.125V/1.6µS = 78mV/µS. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
Vslope
Therefore
Cslope min
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or
between 68 and 33pF.
Over and Under Voltage Monitor
The OV and UV signals are inputs to a window comparator
used to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range,
a shutdown fault occurs. For OV faults, the supply current,
I
is attempted. If the fault is cleared, a soft start cycle begins.
Cslope
CC
, is reduced to 200µA for ~ 295ms at which time recovery
(
CURRENT SENSE SIGNAL
=
=
Current Sense Signal
1
-- - 0.078 2.4
2
4.24
•
)
=
×10
4.24
–
6
•
×10
•
------------------- -
Vslope
–
ton
6
=
•
FIGURE 5.
94mV
2.4
-----------------------
TIME
0.094
10
Time
×10
DOWNSLOPE
–
F
Downslope
6
≈
110pF
(EQ. 6)
(EQ. 7)
(EQ. 8)
ISL6721
Otherwise another shutdown cycle occurs. A UV condition
also results in a shutdown fault, but the device does not
enter the low power mode and no restart delay occurs when
the fault clears.
A resistor divider between Vin and LGND to each input
determines the operational thresholds. The UV threshold
has a fixed hysteresis of 75mV nominal.
Over Current Operation
The over current threshold level is set by the voltage applied
at the ISET pin. Setting the over current level may be
accomplished by using a resistor divider network from VREF
to LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
Over current delayed shutdown is enabled once the soft
start cycle is complete. If an over current condition is
detected, the soft start charging current source is disabled
and the discharging current source is enabled. The soft start
capacitor is discharged at a rate of 40µA. At the same time a
50µS retriggerable one-shot timer is activated. It remains
active for 50µS after the over current condition stops. The
soft start discharge cycle cannot be reset until the one-shot
timer becomes inactive. If the soft start capacitor discharges
by more then 0.125V to 4.375V, the output is disabled and
the soft start capacitor is discharged. The output remains
disabled and I
A new soft start cycle is then initiated. The shutdown and
restart behavior of the OC protection is often referred to as
hic-cup operation due to its repetitive start-up and shutdown
characteristic.
If the over current condition ceases at least 50µS prior to the
soft start voltage reaching 4.375V, the soft start charging
and discharging currents revert to normal operation and the
soft start voltage is allowed to recover.
Hic-cup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
voltage, or about 1.5V.
Leading Edge Blanking
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the over
current comparator.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, the UV input falls below 1.45V, or the
junction temperature of the die exceeds ~130
Fault is detected the GATE output is disabled and the soft
start capacitor is quickly discharged. When the Fault
CC
drops to 200µA for approximately 295ms.
o
C. When a