CT2553-PCB Aeroflex Circuit Technology, CT2553-PCB Datasheet - Page 4

• Manufacturer Part Number: CT2553-PCB
• Description: Advanced Integrated Mux Aim Hybrid For Mil-std-1553 / Sae-as15531 In Pcb Style
• Manufacturer: Aeroflex Circuit Technology

GENERAL
The CT2553-PCB is a complete MIL-STD-1553 bus
interface unit containing dual low-power transceivers;
Bus Controller (BC), Remote Terminal (RTU), and Bus
Monitor (MT) protocol logic; 8K x 16-bit pseudo dual
port RAM; and memory management arbitration control
circuitry. The host processor interface consists of
standard control and interrupt signals, memory expansion
capability and non-multiplexed address and data buses.
Control of the CT2553-PCB is accomplished entirely
through the use of three internal registers and the shared
RAM. Transfers to and from the CT2553-PCB are
executed on a word-by-word basis ensuring minimal wait
time if contention occurs.
The specific mods of operation (1553 BC/RT/MT) is
software programmable. Memory is configured into
unique control and data block areas based on the 1553
mode of operation. External registers are also supported
by the CT2553-PCB for manipulation of user data. In
addition, the CT2553-PCB provides dynamic, online and
software initiated self-test capabilities.
INTERFACING
The CT2553-PCB is compatible with most common
microprocessors including, but not limited to, the
Motorola 680 x 0, the Intel 808x, Zilog Z800x and
MIL-STD-1750 processors.
Interfacing the CT2553-PCB to the MIL-STD-1553 Data
Bus requires two Q1553-2 pulse transformers and an
external 16 MHz clock (See Figure 2). Tri-state buffers
are used to isolate the CPU's data and address lines.
External RAM can be used instead of or in conjunction
with the CT2553-PCB's internal 8K x 16 bits. The
external RAM used by the CT2553-PCB can be any
standard static memory with an access time of < 55ns.
The external RAM can be expanded to 64K x 16.
Two control signals,
MEMENMA-OUT
standard memory I/O signals for internal/external
memory access control (See Figures 3 - 5).
and
Memory Only configuration. Memory
generated for configurations using external memory.
SCDCT2553PCB Rev A Preliminary 7/13/06
MEMEN-IN
(pin 31) are provided in addition to the
should be tied together for Internal
MEMENA-IN
CS
(pin 69) and
signals can be
MEMEN-OUT
4
MEMORY MANAGEMENT
Memory can be configured to support two AREAs (A
and B), each with an independent sequential stack and
pointers for manipulating 1553 message and control data.
The CPU can access the shared RAM while 1553
message transfers are taking place. Arbitration of the
RAM is automatically implemented in a manner
transparent to the subsystem (See Figures 28-31).
Variable Length DATA BLOCKS are also stored in the
shared RAM and can be addressed by setting pointers
residing in Area A, Area B or both.
For BC/RTU operation, each area contains a Descriptor
Stack and Stack Pointer (See Figures 6 and 7). BC
operation further maintains a Message Count for each
area (number of 1553 messages per frame). RTU
operation maintains a data block address Look-Up Table
for each area. MT operation utilizes a single Stack
Pointer to indicate the starting address for storage of
received words and associated identification Words.
CURRENT AREA ASSIGNMENT/SWAING
Current area status (currently available to the 1553
terminal) is Software programmable by the host; the
unassigned area automatically assumes non-current area
status. Both areas are always addressable by the host.
Swapping of the Current Area can be done following
message transfers for user operations such as exception
handling or multiple buffering of 1553 data.
The host selects the Current Area by writing to the
CT2553-PCB’s Configuration Register with bit 13 set to
the appropriate logic level (0 for area A or 1 for area B).
Internal circuitry ensures that the swapping of Current
Area Status does not occur during an ongoing message
transfer (See Configuration Register).
DESCRIPTOR STACK (BC/RTU)
The DESCRIPTOR STACK (DS) is divided into 64
entries. Each stack entry contains four words which refer
to one 1553 message. The Block Status Word (BSW)
indicates the physical bus on which the message was
received (RTU mode), reports whether or not an error
was detected during message transfer and indicates
message completion (See Figure 8).
The user-supplied Time Tag word is loaded at the start of
a message transfer and is updated at the end of the
transfer (See Time Tagging).
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